Quantum well stacks for quantum dot devices

Patent metadata

Field	Value
Publication number	US-11677017-B2
Application number	US-202117472015-A
Country	US
Kind code	B2
Filing date	Sep 10, 2021
Priority date	Sep 28, 2017
Publication date	Jun 13, 2023
Grant date	Jun 13, 2023

Abstract

Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include a (111) silicon substrate, a (111) germanium quantum well layer above the substrate, and a plurality of gates above the quantum well layer. In some embodiments, a quantum dot device may include a silicon substrate, an insulating material above the silicon substrate, a quantum well layer above the insulating material, and a plurality of gates above the quantum well layer.

First claim

The invention claimed is:

1. A quantum dot device, comprising:
a substrate, wherein the substrate includes (111) silicon;
a quantum well stack on the substrate, wherein the quantum well stack includes a quantum well layer that includes (111) germanium;
a first doped region in a first portion of the quantum well stack;
a second doped region in a second portion of the quantum well stack;
a continuous portion of the quantum well stack between the first doped region and the second doped region, wherein a dopant concentration of the continuous portion of the quantum well stack between the first doped region and the second doped region is lower than a dopant concentration of the first doped region and a dopant concentration of the second doped region; and
a plurality of gates above the continuous portion of the quantum well stack between the first doped region and the second doped region, wherein the quantum well layer is between the plurality of gates and the substrate.

2. The quantum dot device of claim 1 , further comprising a first gate and a second gate, in addition to the plurality of gates, wherein:
a first portion of the first gate is above the first doped region and a second portion of the first gate is above a first portion of the continuous portion of the quantum well stack between the first doped region and the second doped region, and
a first portion of the second gate is above the second doped region and a second portion of the second gate is above a second portion of the continuous portion of the quantum well stack between the first doped region and the second doped region.

3. The quantum dot device of claim 2 , wherein, when measured along a line between the first doped region and the second doped region, a dimension of the first gate or a dimension of the second gate is greater than a dimension of at least one of the plurality of gates.

4. The quantum dot device of claim 2 , wherein, when measured along a line between the first doped region and the second doped region, a length of an individual gate of the first gate and the second gate is greater than a length of an individual gate of the plurality of gates.

5. The quantum dot device of claim 1 , wherein the continuous portion of the quantum well stack between the first doped region and the second doped region is a quantum dot formation region where one or more quantum dots are to form during operation of the quantum dot device.

6. The quantum dot device of claim 1 , further comprising an oxide material between the quantum well layer and the substrate, wherein the oxide material has a thickness between 5 nanometers and 200 nanometers.

7. The quantum dot device of claim 1 , wherein:
the quantum dot device is a quantum computing device that includes a quantum processing device and a non-quantum processing device, coupled to the quantum processing device,
the quantum processing device includes the substrate, the quantum well stack, and the plurality of gates, and
the non-quantum processing device is to control voltages applied to the plurality of gates.

8. The quantum dot device of claim 7 , further comprising:
a cooling apparatus to maintain a temperature of the quantum processing device below 5 degrees Kelvin.

9. A quantum dot device, comprising:
a substrate, wherein the substrate includes (111) silicon;
a quantum well stack on the substrate, wherein the quantum well stack includes a quantum well layer that includes (111) germanium; and
a plurality of gates above the quantum well stack, wherein the quantum well layer is between the plurality of gates and the substrate,
wherein the quantum well layer is relaxed.

10. The quantum dot device of claim 9 , further comprising an insulating material between the quantum well layer and the substrate.

11. The quantum dot device of claim 10 , wherein the insulating material includes an oxide.

12. The quantum dot device of claim 10 , wherein the insulating material is relaxed.

13. The quantum dot device of claim 10 , wherein the insulating material is strained.

14. The quantum dot device of claim 9 , wherein the quantum well stack further includes a buffer layer between the substrate and the quantum well layer, and the buffer layer includes germanium tin or a group III-group V material or (111) germanium.

15. The quantum dot device of claim 9 , wherein:
the quantum dot device is a quantum computing device that includes a quantum processing device and a non-quantum processing device, coupled to the quantum processing device,
the quantum processing device includes the substrate, the quantum well stack, and the plurality of gates, and
the non-quantum processing device is to control voltages applied to the plurality of gates.

16. The quantum dot device of claim 15 , further comprising:
a cooling apparatus to maintain a temperature of the quantum processing device below 5 degrees Kelvin.

17. A quantum dot device, comprising:
a substrate, wherein the substrate includes (111) silicon;
a quantum well stack on the substrate, wherein the quantum well stack includes a quantum well layer that includes (111) germanium; and
a plurality of gates above the quantum well stack, wherein the quantum well layer is between the plurality of gates and the substrate,
wherein a distance between adjacent gates of the plurality of gates is between 1 and 10 nanometers.

18. The quantum dot device of claim 17 , wherein the quantum well layer is relaxed.

19. The quantum dot device of claim 17 , wherein the quantum well stack further includes a buffer layer between the substrate and the quantum well layer, and the buffer layer includes germanium tin or a group III-group V material or (111) germanium.

20. The quantum dot device of claim 17 , wherein:
the quantum dot device is a quantum computing device that includes a quantum processing device and a non-quantum processing device, coupled to the quantum processing device,
the quantum processing device includes the substrate, the quantum well stack, and the plurality of gates, and
the non-quantum processing device is to control voltages applied to the plurality of gates.

21. A quantum dot device, comprising:
a substrate, wherein the substrate includes silicon;
a quantum well stack on the substrate, wherein the quantum well stack includes an insulating material and a quantum well layer, wherein the insulating material is between the substrate and the quantum well layer and wherein the insulating material is relaxed; and
a plurality of gates above the quantum well stack, wherein the quantum well layer is between the plurality of gates and the substrate.

22. The quantum dot device of claim 21 , wherein the quantum well stack further includes a buffer layer between the substrate and the quantum well layer, and the buffer layer includes germanium tin or a group III-group V material or ( 111 ) germanium.

23. The quantum dot device of claim 21 , further comprising:
a first doped region in a first portion of the quantum well stack;
a second doped region in a second portion of the quantum well stack; and
a continuous portion of the quantum well stack between the first doped region and the second doped region, wherein a dopant concentration of the continuous portion of the quantum well stack between the first doped region and the second doped region is lower than a dopant concentration of the first doped region and a dopant concentration of the second doped region,
wherein the plurality of gates is above t

Assignees

• Intel Corp

Inventors

• Pillarisetty Ravi
• Le Van H
• Thomas Nicole K
• George Hubert C
• Roberts Jeanette M
• Amin Payam
• Yoscovits Zachary R
• Caudillo Roman
• Clarke James S
• Kotlyar Roza
• Singh Kanwaljit

Classifications

• H01L29/66984

  Electricity · mapped topic

• H01L29/82

  Electricity · mapped topic

• H01L27/1203

  Electricity · mapped topic

• G06N10/00

  Quantum computing, i.e. information processing based on quantum-mechanical phenomena · CPC title

• H01L21/823475

  Electricity · mapped topic