Semiconductor structure and fabrication method thereof

Patent metadata

Field	Value
Publication number	US-11676865-B2
Application number	US-202117243776-A
Country	US
Kind code	B2
Filing date	Apr 29, 2021
Priority date	May 18, 2020
Publication date	Jun 13, 2023
Grant date	Jun 13, 2023

Abstract

Semiconductor structures and fabrication methods thereof are provided. The method includes providing a substrate; forming a stacked material structure on the substrate; and forming trenches in the stacked material structure. Bottoms of the trenches are in the first material layer, the trenches are arranged along a first direction and form an initial stacked structure sequentially including an initial first layer, an initial second layer and an initial third layer. The method also includes etching the initial third layer to form transitional third layers arranged along a second direction perpendicular to the first direction; removing a portion of the initial first layer and a portion of the initial second layer of the initial stacked structure at two sides along the second direction to form a stacked structure including a first layer, a second layer and the transitional third layers; and forming a gate structure.

First claim

What is claimed is:

1. A method for forming a semiconductor structure, comprising:
providing a substrate;
forming a stacked material structure, including a first material layer, a second material layer on the first material layer, and a third material layer on the second material layer, on the substrate;
forming a plurality of trenches in the stacked material structure, wherein bottoms of the plurality of trenches are in the first material layer, the plurality of trenches are arranged along a first direction that is parallel to a surface of the substrate and form an initial stacked structure, and the initial stacked structure includes an initial first layer, an initial second layer on the initial first layer, and an initial third layer on the initial second layer;
etching the initial third layer to form a plurality of transitional third layers, wherein the plurality of transitional third layers are arranged along a second direction that is parallel to the surface of the substrate and the second direction is perpendicular to the first direction;
after forming the plurality of transitional third layers, removing a portion of the initial first layer and a portion of the initial second layer of the initial stacked structure at two sides along the second direction to form a stacked structure, wherein the stacked structure includes a first layer, a second layer on the first layer, and the plurality of transitional third layers on the second layer; and
forming a gate structure on a portion of the stacked structure.

2. The method according to claim 1 , wherein:
the first layer includes a first portion and a second portion on the first portion;
the first portion has a first projection on the substrate;
the second portion has a second projection on the substrate;
an area of the first projection is greater than an area of the second projection; and
the second projection is within the first projection.

3. The method according to claim 1 , after forming the initial stacked structure and before forming the plurality of transitional third layers, further comprising:
forming an insulation structure in the plurality of trenches;
wherein the isolation structure exposes sidewall surfaces of the initial third layer, and a top surface of the isolation structure is lower than, or levels with a bottom surface of the initial third layer.

4. The method according to claim 3 , wherein forming the gate structure on the portion of the stacked structure comprises:
forming the gate structure on a surface of the stacked structure exposed by the isolation structure.

5. The method according to claim 3 , wherein forming the plurality of transitional third layers comprises:
forming a first liner layer on the isolation structure, wherein the first liner layer is also on a top surface and sidewall surfaces of the initial third layer;
forming a second mask layer on the first liner layer, wherein patterns of the second mask layer are arranged along the second direction;
etching the initial third layer using the second mask layer as a mask until a surface of the second layer is exposed to form the plurality of transitional third layers; and
removing the second mask layer and the first liner layer after forming the plurality of transitional third layers.

6. The method according to claim 5 , wherein forming the isolation structure comprises:
forming an isolation material layer on the initial stacked structure;
planarizing the isolation material layer until a top surface of the initial stacked structure is exposed to form an initial isolation layer;
etching back the initial isolation layer until the initial third layer is completely exposed to form a transitional isolation structure; and
removing portions of the transitional isolation structure on sidewall surfaces of the initial first layer and the initial second layer along the second direction to form the isolation structure.

7. The method according to claim 3 , wherein:
the isolation structure includes a dielectric material; and
the dielectric material includes silicon oxide.

8. The method according to claim 1 , wherein:
the gate structure includes a gate dielectric layer on a surface of the second layer and a gate electrode layer on the gate dielectric layer.

9. The method according to claim 8 , wherein:
the gate structure also includes an interlayer dielectric layer between the second layer and the gate dielectric layer and a work function layer between the gate dielectric layer and the gate electrode layer.

10. The method according to claim 1 , after forming the stacked structure, further comprising:
thinning the plurality of transitional third layers along a direction perpendicular to sidewall surfaces of the plurality of transitional third layers.

11. The method according to claim 10 , wherein thinning the plurality of transitional third layers comprises:
oxidizing surfaces of the plurality of transitional third layers to form an oxide layer; and
removing the oxide layer.

12. The method according to claim 1 , wherein forming the initial stacked structure comprises:
forming a first mask layer on the stacked material structure, wherein patterns of the first mask layer are arranged along the first direction; and
etching the third material layer, the second material layer, and a portion of the first material layer using the first mask layer as a mask to form the initial stacked structure on the substrate.

13. The method according to claim 1 , wherein removing the portions of the initial first layer and the initial second layer of the initial stacked structure at the two sides along the second direction comprises:
forming a second liner layer on the initial second layer, wherein the second liner layer is on top surfaces and sidewall surfaces of the plurality of transitional third layers;
forming a third mask layer on the second liner layer, wherein the third mask layer exposes portions of a top surface of the second layer at the two sides along the second direction;
etching the second liner layer, the initial second layer and the initial first layer using the third mask layer as a mask to form the stacked structure; and
removing the second liner layer and the third mask layer after forming the stacked structure.

14. The method according to claim 1 , wherein:
a material of the first layer includes a semiconductor material and the semiconductor material includes one of silicon and silicon germanium;
a material of the second layer includes a semiconductor material and the semiconductor material includes one of silicon and silicon germanium; and
a material of the plurality of transitional third layers includes a semiconductor material and the semiconductor material includes one of silicon and silicon germanium.

15. The method according to claim 1 , wherein:
the first layer includes a first type of ions and the first type of ions include N-type of ions or P-type of ions;
the second layer includes a second type of ions and the second type of ions include N-type of ions or P-type of ions;
the N-type of ions include phosphor ions or arsenic ions; and
the P type of ions include boron ions or boron fluoride ions.

16. The method according to claim 15 , wherein:
an ion type of the first type of ions is opposite to an ion type of the second type of ions.

17. The method according to claim 1 , wherein:
the plurality of trenches pass through the initial stacked structure along the second direction that is parallel to the surface of the substrate; and
the second direction is perpendicular to the first direct

Assignees

• Semiconductor Mfg Int Shanghai Corp
• Semiconductor Mfg Int Beijing Corp

Inventors

• Zhang Haiyang
• Zhao Zhenyang
• Zhang Enning

Classifications

• H01L21/823481

  Electricity · mapped topic

• H01L21/823431 Primary

  Electricity · mapped topic

• H01L27/0886

  Electricity · mapped topic

• H10D84/834

  comprising FinFETs · CPC title

• H10D84/0151

  Manufacturing their isolation regions · CPC title