Machine learning based layout nudging for design rule compliance

Patent metadata

Field	Value
Publication number	US-11675960-B2
Application number	US-202117516476-A
Country	US
Kind code	B2
Filing date	Nov 1, 2021
Priority date	Nov 1, 2021
Publication date	Jun 13, 2023
Grant date	Jun 13, 2023

Abstract

Embodiments of a system and method for generating integrated circuit layouts are described herein. A computer implemented method for generating integrated circuit layouts includes receiving a first layout for an integrated circuit, segmenting the first layout into a plurality of different patches, each patch of the plurality of patches describing a discrete portion of the first layout, identifying a non-compliant patch of the plurality of patches, the non-compliant patch violating a design rule governing the manufacture of the integrated circuit, generating a transformation of the non-compliant patch using a machine learning model, and generating a second layout using the transformation and the first layout, where the second layout is compliant with the design rule.

First claim

What is claimed is:

1. A computer implemented method for generating integrated circuit layouts, the computer implemented method comprising:
receiving a first layout for an integrated circuit;
segmenting the first layout into a plurality of different patches, each patch of the plurality of patches describing a discrete portion of the first layout;
identifying a non-compliant patch of the plurality of patches, the non-compliant patch violating a design rule governing the manufacture of the integrated circuit;
using a machine learning model to output a transformation of the non-compliant patch, wherein the transformation describes a modification of the first layout; and
generating a second layout using the transformation and the first layout, wherein the second layout is compliant with the design rule.

2. The computer implemented method of claim 1 , wherein the non-compliant patch is a first patch, the transformation is a first transformation, the design rule is a first design rule, and wherein the computer implemented method further comprises:
identifying a second patch of the plurality of patches, the second patch violating a second design rule governing the manufacture of the integrated circuit, wherein the second patch is different from the first patch;
using the machine learning model to output a second transformation of the second patch; and
generating a global transformation using the first transformation and the second transformation,
wherein generating the second layout comprises modifying the first layout using the global transformation.

3. The computer implemented method of claim 2 , wherein generating the global transformation comprises:
inputting the first transformation and the second transformation into a rules-based model configured to preserve a function of the integrated circuit;
selecting, by the rules-based model, to include the first transformation, the second transformation, or both the first transformation and the second transformation in the global transformation; and
generating the global transformation using the rules-based model.

4. The computer implemented method of claim 1 , wherein the non-compliant patch defines a plurality of polygons, and wherein the transformation describes a modification of a polygon of the plurality of polygons relative to the first layout.

5. The computer implemented method of claim 4 , wherein the transformation describes a displacement of an edge of the polygon, an introduction of a gap in the edge, or an introduction of a vertex in the edge.

6. The computer implemented method of claim 1 , wherein the machine learning model is a convolutional neural network model, and wherein using the machine learning model to output the transformation comprises:
inputting an image of the non-compliant patch to the convolutional neural network model trained to predict the transformation from the image; and
predicting the transformation using the convolutional neural network model.

7. The computer implemented method of claim 1 , further comprising training the machine learning model, the training comprising:
accessing a training set of design pairs, each design pair comprising a compliant patch, a non-compliant patch, and a perturbation vector describing a perturbation of the compliant patch producing the non-compliant patch;
inputting a non-compliant image of the non-compliant patch to the machine learning model;
predicting an inverse transformation using the machine learning model;
generating a training signal using the inverse transformation and the perturbation vector; and
modifying one or more learned parameters of the machine learning model using the training signal.

8. The computer implemented method of claim 7 , further comprising:
receiving a second layout file associated with a set of design rules for an integrated circuit manufacturing process;
defining a plurality of compliant patches using the second layout file, each compliant patch of the plurality of compliant patches in compliance with the set of design rules;
generating a perturbed patch using a compliant patch of the plurality of compliant patches;
determining that the perturbed patch violates one or more design rules of the set of design rules;
defining the perturbation vector linking the compliant patch and the perturbed patch; and
generating a design pair of the set of design pairs using the compliant patch, the perturbed patch, and the perturbation vector.

9. The computer implemented method of claim 1 , wherein the non-compliant patch describes a physical region of the integrated circuit.

10. The computer implemented method of claim 1 , wherein the non-compliant patch describes a physical implementation of a logical function described by the first layout and implemented by the integrated circuit.

11. The computer implemented method of claim 1 , wherein the transformation describes a layer of the integrated circuit affected by the transformation, a location of the transformation in the layer, and an extent of the transformation.

12. The computer implemented method of claim 11 , wherein the transformation is addressed at an edge of a polygon of the non-compliant patch.

13. The computer implemented method of claim 1 , wherein the first layout and second layout are functionally consistent.

14. The computer implemented method of claim 1 , further comprising outputting the second layout to a display as part of an interactive design environment.

15. The computer implemented method of claim 1 , wherein identifying the non-compliant patch comprises checking the plurality of patches against the design rule using a design rule checking engine.

16. At least one machine-accessible storage medium that provides instructions that, when executed by a machine, will cause the machine to perform operations comprising:
receiving a first layout for an integrated circuit;
segmenting the first layout into a plurality of different patches, each patch of the plurality of patches describing a discrete portion of the first layout;
identifying a non-compliant patch of the plurality of patches, the non-compliant patch violating a design rule governing the manufacture of the integrated circuit;
using a machine learning model to output a transformation of the non-compliant patch, wherein the transformation describes a modification of the first layout; and
generating a second layout using the transformation and the first layout, wherein the second layout is compliant with the design rule.

17. The at least one machine-accessible storage medium of claim 16 , wherein the non-compliant patch is a first patch, the transformation is a first transformation, the design rule is a first design rule, and wherein the instructions, when executed by the machine, further cause the machine to perform operations comprising:
identifying a second patch of the plurality of patches, the second patch violating a second design rule governing the manufacture of the integrated circuit, wherein the second patch is different from the first patch;
using the machine learning model to output a second transformation of the second patch; and
generating a global transformation using the first transformation and the second transformation,
wherein generating the second layout comprises modifying the first layout using the global transformation.

18. The at least one machine-accessible storage medium of claim 17 , wherein generating the global transformation comprises:
inputting the first transformation and the second transformation into a rules-based model configured to

Assignees

• X Dev Llc

Inventors

• Apte Raj
• Behroozi Cyrus
• Heal Kathryn
• Lewis Owen
• Pan Zhigang
• Ruic Dino

Classifications

• G06F30/323

  Translation or migration, e.g. logic to logic, hardware description language [HDL] translation or netlist translation · CPC title

• G06F30/27

  using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model · CPC title

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06N3/0464

  Convolutional networks [CNN, ConvNet] · CPC title

• G06F30/392 Primary

  Floor-planning or layout, e.g. partitioning or placement · CPC title