Point-to-point module connection interface for integrated circuit generation

Patent metadata

Field	Value
Publication number	US-11675959-B2
Application number	US-202117504030-A
Country	US
Kind code	B2
Filing date	Oct 18, 2021
Priority date	Jun 5, 2019
Publication date	Jun 13, 2023
Grant date	Jun 13, 2023

Abstract

Systems and methods are disclosed for generation and testing of integrated circuit designs with point-to-point connections between modules. These may allow for the rapid design and testing (e.g. silicon testing) of processors and SoCs. For example, type parameterization may be used to generate point-to-point connections in a flexible manner. For example, a point-to-point connection between the source module and the sink module that includes one or more named wires specified by bundle type may be automatically generated based on using the bundle type as a type parameterization input. For example, these system and methods may be used to rapidly connect a custom processor design, including one or more IP cores, to a standard input/output shell for a SoC design to facilitate rapid silicon testing of the custom processor design.

First claim

What is claimed is:

1. A method comprising:
accessing an indication of a source module of an integrated circuit design;
accessing an indication of a sink module of the integrated circuit design;
accessing an indication of a bundle type, wherein the bundle type specifies one or more named wires;
automatically generating, based on using the bundle type as a type parameterization input, a point-to-point connection between the source module and the sink module that includes the one or more named wires specified by the bundle type; and
generating a register-transfer level data structure for the integrated circuit design including the source module, the sink module, and the point-to-point connection.

2. The method of claim 1 , wherein automatically generating the point-to-point connection between the source module and the sink module comprises:
automatically generating input/output ports for modules between the source module and the sink module at multiple levels of a register-transfer level module hierarchy of the integrated circuit design.

3. The method of claim 1 , wherein automatically generating the point-to-point connection between the source module and the sink module comprises:
using auto-punching to transcend multiple levels of a register-transfer level module hierarchy of the integrated circuit design when connecting the one or more named wires specified by the bundle type between the source module and the sink module.

4. The method of claim 1 , wherein automatically generating the point-to-point connection between the source module and the sink module comprises:
invoking a Scala method that takes the bundle type as a type parameter.

5. The method of claim 1 , wherein the bundle type specifies respective widths of the one or more named wires and the point-to-point connection is automatically generated based on the respective widths of the one or more named wires.

6. The method of claim 1 , wherein the bundle type specifies respective directionalities of the one or more named wires and the point-to-point connection is automatically generated based on the respective directionalities of the one or more named wires.

7. The method of claim 1 , wherein the source module includes a processor core and the sink module is a component of an input/output shell for a system-on-a-chip design.

8. The method of claim 1 , comprising:
generating a physical design data structure for an integrated circuit based on the register-transfer level data structure;
invoking fabrication of the integrated circuit based on the physical design data structure;
invoking tests of the fabricated integrated circuit to obtain a set of test results; and
transmitting, storing, or displaying the set of test results.

9. The method of claim 1 , comprising:
generating a physical design data structure for an integrated circuit based on the register-transfer level data structure;
generating a software development kit for the integrated circuit based on the register-transfer level data structure;
generating a test plan for the integrated circuit;
invoking tests for the integrated circuit based on the test plan, the register-transfer level data structure, the software development kit, and the physical design data structure to obtain test results; and
transmitting, storing, or displaying a design data structure based on the register-transfer level data structure, the software development kit, the physical design data structure, and the test results.

10. A system comprising:
a network interface;
a memory; and
a processor, wherein the memory includes instructions executable by the processor to cause the system to:
access an indication of a bundle type, wherein the bundle type specifies one or more named wires;
automatically generate, based on using the bundle type as a type parameterization input, a point-to-point connection between a source module of an integrated circuit design and a sink module of the integrated circuit design that includes the one or more named wires specified by the bundle type; and
generate a register-transfer level data structure for the integrated circuit design including the source module, the sink module, and the point-to-point connection.

11. The system of claim 10 , wherein the memory includes instructions executable by the processor to cause the system to:
automatically generate input/output ports for modules between the source module and the sink module at multiple levels of a register-transfer level module hierarchy of the integrated circuit design.

12. The system of claim 10 , wherein the memory includes instructions executable by the processor to cause the system to:
use auto-punching to transcend multiple levels of a register-transfer level module hierarchy of the integrated circuit design when connecting the one or more named wires specified by the bundle type between the source module and the sink module.

13. The system of claim 10 , wherein the memory includes instructions executable by the processor to cause the system to:
invoke a Scala method that takes the bundle type as a type parameter.

14. The system of claim 10 , wherein the bundle type specifies respective widths of the one or more named wires and the point-to-point connection is automatically generated based on the respective widths of the one or more named wires.

15. The system of claim 10 , wherein the bundle type specifies respective directionalities of the one or more named wires and the point-to-point connection is automatically generated based on the respective directionalities of the one or more named wires.

16. The system of claim 10 , wherein the source module includes a processor core and the sink module is a component of an input/output shell for a system-on-a-chip design.

17. A non-transitory computer-readable storage medium that includes instructions that, when executed by a processor, facilitate performance of operations comprising:
accessing an indication of a source module of an integrated circuit design;
accessing an indication of a sink module of the integrated circuit design;
accessing an indication of a bundle type, wherein the bundle type specifies one or more named wires;
automatically generating, based on using the bundle type as a type parameterization input, a point-to-point connection between the source module and the sink module that includes the one or more named wires specified by the bundle type; and
generating a register-transfer level data structure for the integrated circuit design including the source module, the sink module, and the point-to-point connection.

18. The non-transitory computer-readable storage medium of claim 17 , wherein automatically generating the point-to-point connection between the source module and the sink module comprises:
automatically generating input/output ports for modules between the source module and the sink module at multiple levels of a register-transfer level module hierarchy of the integrated circuit design.

19. The non-transitory computer-readable storage medium of claim 17 , wherein the bundle type specifies respective widths of the one or more named wires and the point-to-point connection is automatically generated based on the respective widths of the one or more named wires.

20. The non-transitory computer-readable storage medium of claim 17 , wherein the bundle type specifies respective directionalities of the one or more named wires and the point-to-point connection is automatically generated based on the respective directionalities of the one

Assignees

• Sifive Inc

Inventors

• Wachs Megan
• Cook Henry
• Terpstra Wesley Waylon

Classifications

• G06F30/331

  with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation · CPC title

• G06F30/32 Primary

  Circuit design at the digital level (reconfigurable circuits G06F30/34) · CPC title

• G06F2111/20

  Configuration CAD, e.g. designing by assembling or positioning modules selected from libraries of predesigned modules · CPC title

• G06F2115/10

  Processors · CPC title

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title