Reset crossing and clock crossing interface for integrated circuit generation

Patent metadata

Field	Value
Publication number	US-11675945-B2
Application number	US-202217734332-A
Country	US
Kind code	B2
Filing date	May 2, 2022
Priority date	Jul 9, 2019
Publication date	Jun 13, 2023
Grant date	Jun 13, 2023

Abstract

Systems and methods are disclosed for generation and testing of integrated circuit designs with clock crossings between clock domains and reset crossings between reset domains. These may allow for the rapid design and testing (e.g. silicon testing) of processors and SoCs. Clock crossings may be automatically generated between modules, inferring the values of design parameters, such as a signaling protocol (e.g. a bus protocol), directionality, and/or a clock crossing type (e.g., synchronous, rational divider, or asynchronous), of a clock crossing. Reset crossings may be automatically generated in a similar manner. For example, implicit classes may be used to generate clock crossings or reset crossings in a flexible manner. For example, these system and methods may be used to rapidly connect a custom processor design, including one or more IP cores, to a standard input/output shell for a SoC design to facilitate rapid silicon testing of the custom processor design.

First claim

What is claimed is:

1. A non-transitory computer-readable storage medium that includes instructions that, when executed by a processor, facilitate performance of operations comprising:
accessing a register-transfer level data structure for an integrated circuit design;
receiving a command to generate a reset crossing between a first module of the register-transfer level data structure and a second module of the register-transfer level data structure;
responsive to the command, automatically determining a signaling protocol identifier for the reset crossing based on data of the second module;
responsive to the command, automatically determining a directionality for the reset crossing based on data of the second module; and
responsive to the command, automatically generating the reset crossing between the first module and the second module based on the signaling protocol identifier and based on the directionality to obtain a modified register-transfer level data structure.

2. The non-transitory computer-readable storage medium of claim 1 , wherein the instructions include instructions that, when executed by a processor, facilitate performance of operations comprising:
responsive to the command, automatically determining a reset crossing type for the reset crossing based on a reset domain type of the first module and based on a reset domain type of the second module, wherein the reset crossing is automatically generated based on the reset crossing type.

3. The non-transitory computer-readable storage medium of claim 2 , wherein the reset domain type of the first module indicates a first reset duration in clock cycles, the reset domain type of the second module indicates a second reset duration in clock cycles, and the reset crossing type indicates a difference between the first reset duration and the second reset duration.

4. The non-transitory computer-readable storage medium of claim 1 , wherein the command includes a parameter specifying a reset crossing type and the reset crossing is automatically generated based on the reset crossing type specified by the command.

5. The non-transitory computer-readable storage medium of claim 1 , wherein automatically generating the reset crossing comprises:
generating register-transfer level data implementing logic to suppress one or more outputs of the first module in accordance with a bus protocol identified by the signaling protocol identifier during a reset period for the first module.

6. The non-transitory computer-readable storage medium of claim 1 , wherein automatically generating the reset crossing comprises:
generating register-transfer level data implementing logic to stretch a reset signal to meet a minimum reset duration of the first module.

7. The non-transitory computer-readable storage medium of claim 1 , wherein automatically generating the reset crossing comprises:
using an implicit class that is invoked using the signaling protocol identifier.

8. The non-transitory computer-readable storage medium of claim 1 , wherein the second module is a bus module.

9. The non-transitory computer-readable storage medium of claim 1 , wherein the first module includes an IP core and the second module is a component of an input/output shell for a system-on-a-chip design.

10. The non-transitory computer-readable storage medium of claim 1 , wherein the instructions include instructions that, when executed by a processor, facilitate performance of operations comprising:
generating a physical design data structure for the integrated circuit based on the modified register-transfer level data structure;
invoking fabrication of the integrated circuit based on the physical design data structure;
invoking tests of the fabricated integrated circuit to obtain a set of test results; and
transmitting, storing, or displaying the set of test results.

11. The non-transitory computer-readable storage medium of claim 1 , wherein the instructions include instructions that, when executed by a processor, facilitate performance of operations comprising:
generating a physical design data structure for the integrated circuit based on the modified register-transfer level data structure;
generating a software development kit for the integrated circuit based on the modified register-transfer level data structure;
generating a test plan for the integrated circuit;
invoking tests for the integrated circuit based on the test plan, the modified register-transfer level data structure, the software development kit, and the physical design data structure to obtain a set of test results; and
transmitting, storing, or displaying a design data structure based on the modified register-transfer level data structure, the software development kit, the physical design data structure, and the test results.

12. A system comprising:
a network interface;
a memory; and
a processor, wherein the memory includes instructions executable by the processor to cause the system to:
access a register-transfer level data structure for an integrated circuit design;
receive a command to generate a reset crossing between a first module of the register-transfer level data structure and a second module of the register-transfer level data structure;
responsive to the command, automatically determine a signaling protocol identifier for the reset crossing based on data of the second module;
responsive to the command, automatically determine a directionality for the reset crossing based on data of the second module; and
responsive to the command, automatically generate the reset crossing between the first module and the second module based on the signaling protocol identifier and based on the directionality to obtain a modified register-transfer level data structure.

13. The system of claim 12 , wherein the memory further includes instructions executable by the processor to cause the system to:
responsive to the command, automatically determine a reset crossing type for the reset crossing based on a reset domain type of the first module and based on a reset domain type of the second module, wherein the reset crossing is automatically generated based on the reset crossing type.

14. The system of claim 13 , wherein the reset domain type of the first module indicates a first reset duration in clock cycles, the reset domain type of the second module indicates a second reset duration in clock cycles, and the reset crossing type indicates a difference between the first reset duration and the second reset duration.

15. The system of claim 12 , wherein the command includes a parameter specifying a reset crossing type and the reset crossing is automatically generated based on the reset crossing type specified by the command.

16. The system of claim 12 , wherein automatically generating the reset crossing comprises:
generating register-transfer level data implementing logic to suppress one or more outputs of the first module in accordance with a bus protocol identified by the signaling protocol identifier during a reset period for the first module.

17. The system of claim 12 , wherein automatically generating the reset crossing comprises:
generating register-transfer level data implementing logic to stretch a reset signal to meet a minimum reset duration of the first module.

18. The system of claim 12 , wherein automatically generating the reset crossing comprises:
using an implicit class that is invoked using the signaling protocol identifier.

19. The system of claim 12 , wherein the first module includes an IP core and the seco

Assignees

• Sifive Inc

Inventors

• Cook Henry
• Edgar Ernest L
• Macdonald Ryan
• Terpstra Wesley Waylon

Classifications

• G06F30/3312

  Timing analysis · CPC title

• G06F30/398

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F1/24

  Resetting means · CPC title

• G06F30/396 Primary

  Clock trees · CPC title

• G06F2119/12

  Timing analysis or timing optimisation · CPC title