Serial interfaces with shadow registers, and associated systems, devices, and methods

Patent metadata

Field	Value
Publication number	US-11675589-B2
Application number	US-202117464650-A
Country	US
Kind code	B2
Filing date	Sep 1, 2021
Priority date	Sep 1, 2021
Publication date	Jun 13, 2023
Grant date	Jun 13, 2023

Abstract

Serial interfaces with shadow registers, and associated systems, devices, and methods are described herein. In one embodiment, a serial interface is an IEEE 1500 interface, such as of an interface die of a high bandwidth memory (HBM) device. The IEEE 1500 interface includes (a) a primary wrapper data register (WDR) configured to store first information received in a first wrapper serial input (WSI) signal, (b) a shadow WDR configured to store second information received in a second WSI signal, and (c) a multiplexer. The multiplexer is configured to (i) receive the first information from the primary WDR, (ii) receive the second information from the shadow WDR, and (iii) output the first information or the second information based at least in part on a control signal input into the multiplexer.

First claim

We claim:

1. An IEEE 1500 interface, comprising:
a primary wrapper data register (WDR) configured to store first information received in a first wrapper serial input (WSI) signal;
a shadow WDR configured to store second information received in a second WSI signal;
a multiplexer configured to (a) receive the first information from the primary WDR, (b) receive the second information from the shadow WDR, and (c) output the first information or the second information based at least in part on a control signal input into the multiplexer; and
a counter configured to output the control signal to the multiplexer based at least in part on a value stored by the counter.

2. The IEEE 1500 interface of claim 1 , wherein:
the counter is configured to receive an enable signal having a first state and a second state;
when the enable signal is in the first state, the counter is disabled from updating the value stored by the counter; and
when the enable signal is in the second state, the counter is enabled to update the value stored by the counter.

3. The IEEE 1500 interface of claim 2 , wherein, when the enable signal is in the first state, the multiplexer is configured to output the first information received from the primary WDR.

4. The IEEE 1500 interface of claim 2 , wherein:
the counter is further configured to receive an update signal;
the update signal includes an IEEE 1500 wrapper serial port update (UPDATEWR) signal; and
when the enable signal is in the second state, the counter is configured to update the value stored by the counter each time the UPDATEWR signal is asserted in accordance with a transition of an IEEE 1500 wrapper serial portion clock (WRCK) signal.

5. The IEEE 1500 interface of claim 4 , wherein:
the value stored by the counter has a limit; and
when the value reaches the limit, a next update of the value by the counter resets or causes the value to wrap around to an initial state that corresponds to a state of the value when the enable signal is in the first state.

6. The IEEE 1500 interface of claim 1 , wherein the shadow WDR is a duplicate WDR of the primary WDR such that the shadow WDR has a same register size as the primary WDR.

7. The IEEE 1500 interface of claim 1 , wherein:
the shadow WDR is configured to receive an enable signal;
when the enable signal is in a first state, the shadow WDR is disabled from loading the second information included in the second WSI signal; and
when the enable signal is in a second state, the shadow WDR is enabled to load the second information included in the second WSI signal.

8. The IEEE 1500 interface of claim 1 , wherein:
the shadow WDR is a first shadow WDR;
the IEEE 1500 interface further comprises a second shadow WDR configured to store third information received in a third WSI signal; and
the multiplexer is further configured to receive (i) the third information from the second shadow WDR and (ii) output the first information, the second information, or the third information based at least in part on the control signal input into the multiplexer.

9. The IEEE 1500 interface of claim 8 , wherein:
the first shadow WDR is configured to receive a first enable signal that, when asserted, enables the first shadow WDR to load the second information received in the second WSI signal;
the second shadow WDR is configured to receive a second enable signal that, when asserted, enables the second shadow WDR to load the third information received in the third WSI signal; and
the first enable signal is different from the second enable signal.

10. A method, comprising:
loading a first register of a serial interface with first information, wherein the first register has a first output in communication with a first input of a multiplexer of the serial interface;
loading a second register of the serial interface with second information, wherein the second register is a duplicate of the first register, and wherein the second register has a second output in communication with a second input of the multiplexer;
outputting the first information to a mode latch via an output of the multiplexer when a control signal input into the multiplexer is in a first state; and
outputting the second information to the mode latch via the output of the multiplexer when the control signal is in a second state different from the first state.

11. The method of claim 10 , wherein loading the second register includes asserting an enable signal of the second register such that the second register is enabled to load the second information.

12. The method of claim 10 , wherein loading the first register includes loading the first register with the first information in response to receiving instructions for selecting an operational mode of a memory device including the serial interface.

13. The method of claim 10 , further comprising updating a value of a counter such that the control signal transitions from the first state to the second state.

14. The method of claim 13 , wherein updating the value of the counter includes (a) asserting an enable signal such that the counter is enabled to update the value and (b) asserting an IEEE 1500 wrapper serial port update UPDATEWR signal in accordance with a transition of an IEEE 1500 wrapper serial port clock (WRCK) signal.

15. The method of claim 14 , further comprising (a) deasserting the enable signal such that the counter is disabled from updating the value and (b) resetting the value in response to deasserting the enable signal.

16. The method of claim 13 , further comprising holding the control signal in the first state until (a) the counter is enabled and (b) the value of the counter is updated.

17. The method of claim 10 , further comprising:
loading a third register of the serial interface with third information, wherein the third register is another duplicate of the first register, wherein the third information is different from the first information or the second information, and wherein the third register has a third output in communication with a third input of the multiplexer; and
outputting the third information to the mode latch via the output of the multiplexer when the control signal is in a third state different from the first state and the second state.

18. The method of claim 17 , wherein:
loading the second register with the second information includes enabling the second register using a first enable signal; and
loading the third register with the third information includes enabling the third register using a second enable signal different from the first enable signal.

19. A high bandwidth memory (HBM) device, comprising a memory device including one or more core dies, a mode latch, and an interface die having a serial interface, wherein the serial interface comprises:
a primary register configured to store first information received in a first input signal;
a shadow register configured to store second information received in a second input signal;
a multiplexer configured to (a) receive the first information from the primary register, (b) receive the second information from the shadow register, and (c) output the first information or the second information to the mode latch based at least in part on a control signal input into the multiplexer; and
a counter configured to output the control signal to the multiplexer based at least in part on a value stored by the counter.

20. The IEEE 1500 interface of claim 1 , further comprising a wrapper boundary register (WBR) and a wrapper bypass register (WBY)

Assignees

• Micron Technology Inc

Inventors

• Werhane Kevin G
• Miller Daniel S

Classifications

• G06F9/30116 Primary

  Shadow registers, e.g. coupled registers, not forming part of the register space · CPC title

• G06F13/4282 Primary

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F9/30101

  Special purpose registers · CPC title