Frequency tracking loop using a scaled replica oscillator for injection locked oscillators

Patent metadata

Field	Value
Publication number	US-11671105-B2
Application number	US-202217720446-A
Country	US
Kind code	B2
Filing date	Apr 14, 2022
Priority date	Oct 15, 2021
Publication date	Jun 6, 2023
Grant date	Jun 6, 2023

Abstract

An accurate replica oscillator-based frequency tracking loop (FTL) is provided. The replica oscillator used in the FTL can be at a lower frequency and therefore can consume much lower power compared to a main oscillator, such as an injection locked oscillator (ILO). The proposed FTL accurately sets the free running frequency of an ILO across process, voltage and temperature (PVT). Techniques are also provided to compensate the gain and offset error between the replica oscillator and the ILO.

First claim

What is claimed is:

1. An apparatus comprising:
a main oscillator having a main oscillator control input, an injection input and a main oscillator output, and configured to provide at the main oscillator output a main oscillator signal at a first frequency based on a control voltage provided at the main oscillator control input;
a replica oscillator having a replica oscillator control input and a replica oscillator output, and configured to provide at the replica oscillator output a replica oscillator signal at a second frequency based on a control voltage provided at the replica oscillator control input;
a first frequency detector coupled to the main oscillator output and configured to output a main oscillator frequency value that is representative of a frequency of the main oscillator signal;
a second frequency detector coupled to the replica oscillator output and configured to output a replica oscillator frequency value that is representative of a frequency of the replica oscillator signal; and
one or more circuit elements coupled to the replica oscillator control input, wherein the one or more circuit elements are configured to adjust a voltage signal or current signal used to provide the control voltage to the replica oscillator control input based on a difference between the main oscillator frequency value and a frequency value representative of a frequency of an injection clock signal provided at the injection input of the main oscillator, wherein the control voltage causes the replica oscillator to have an oscillator gain that is scaled with respect to an oscillator gain of the main oscillator, wherein an oscillator gain is a ratio of change in free-running oscillator frequency to change in control voltage.

2. The apparatus of claim 1 , wherein the one or more circuit elements include at least one of:
a variable voltage offset circuit configured to add a voltage offset value to the control voltage; and
a variable gain circuit configured to adjust a gain of the control voltage.

3. The apparatus of claim 1 , wherein the first frequency is not equal to the second frequency.

4. The apparatus of claim 3 , wherein the second frequency is substantially less than the first frequency and the second frequency is not a sub-harmonic of the first frequency.

5. The apparatus of claim 1 , further comprising:
a first divider coupled between the main oscillator output and an input of the first frequency detector, wherein the first divider divides a frequency of the main oscillator signal by a first divisor to provide a frequency divided main oscillator signal; and
a second divider coupled between the replica oscillator output and an input of the second frequency detector, wherein the second divider divides a frequency of the replica oscillator signal by a second divisor to provide a frequency divided replica oscillator signal;
wherein:
the first frequency detector is configured to measure a frequency of the frequency divided main oscillator signal to produce the main oscillator frequency value; and
the second frequency detector is configured to measure a frequency of the frequency divided replica oscillator signal to produce the replica oscillator frequency value.

6. The apparatus of claim 5 , further comprising:
a register configured to receive as input the replica oscillator frequency value from the second frequency detector and to provide the replica oscillator frequency value at a register output in response to an enable signal;
a first multiplexer having a first input coupled to the register output and a second input configured to receive a frequency value representative of the injection clock signal, wherein the first multiplexer is configured, based on a select signal, to provide at a first multiplexer output a digital value at the first input or a digital value from the second input;
a second multiplexer having a first input coupled to receive the replica oscillator frequency value and a second input coupled to receive the main oscillator frequency value, wherein the second multiplexer is configured, based on the select signal, to provide at a second multiplexer output a digital value at the first input or a digital value at the second input; and
an adder that includes a first input coupled to the first multiplexer output and a second input coupled to the second multiplexer output.

7. The apparatus of claim 6 , further comprising:
a computation circuit configured to receive as input the main oscillator frequency value, the replica oscillator frequency value and an error value that is based on the difference between the main oscillator frequency value and the frequency value representative of a frequency of an injection clock signal provided at the injection input of the main oscillator, and to generate one or more adjustment controls to the one or more circuit elements to cause the oscillator gain of the replica oscillator to be scaled to the oscillator gain of the main oscillator.

8. The apparatus of claim 7 , wherein the computation circuit is configured to:
upon power up of the apparatus, initiate a frequency tuning phase by setting the enable signal to enable the register output to be provided to the first multiplexer, and setting a value of the select signal that causes the main oscillator to operate in a free-running mode without the injection clock signal, causes the first multiplexer to provide at the first multiplexer output the frequency value representative of the injection clock signal, and that causes the second multiplexer to provide at the second multiplexer output the main oscillator frequency value, wherein the error value is based on a difference between the main oscillator frequency value and the frequency value representative of the injection clock signal; and
when the error value is equal to zero, indicating that the main oscillator frequency value is equal to the frequency value representative of the injection clock signal, unset the enable signal to end the frequency tuning phase and start a calibration phase.

9. The apparatus of claim 8 , wherein the computation circuit is configured, during the calibration phase, to perform a processing loop comprising:
first storing the main oscillator frequency value output by the first frequency detector and the replica oscillator frequency value output by the second frequency detector;
incrementing a digital-to-analog converter output by one least significant bit;
after the incrementing, obtaining a new main oscillator frequency value output by the first frequency detector and a new replica oscillator frequency value output by the second frequency detector;
second storing the new main oscillator frequency value, the new replica oscillator frequency value, a main oscillator change value based on a difference between the new main oscillator frequency value and the main oscillator frequency value, and a replica oscillator change value based on a difference between the new replica oscillator frequency value and the replica oscillator frequency value;
returning the digital-to-analog converter output to a previous value;
computing an oscillator gain error based on a difference between a first ratio and a second ratio, wherein the first ratio is a ratio of the new main oscillator frequency value to the new replica oscillator frequency value, and the second ratio is a ratio of the main oscillator change value to the replica oscillator change value;
evaluating the oscillator gain error to determine whether it is at a minimum;
as long as it is determined that the oscillator gain error is not at a minimum, causing the one or more circuit elements to change an offset or a gain of the voltage signal or current signal to produce the control voltage that is provided

Assignees

• Cisco Tech Inc

Inventors

• Bhat Abhishek
• Nandwana Romesh Kumar
• Lakshmikumar Kadaba
• Hanumolu Pavan Kumar

Classifications

• H03L7/099 Primary

  concerning mainly the controlled oscillator of the loop · CPC title

• H03D5/00

  Circuits for demodulating amplitude-modulated or angle-modulated oscillations at will (H03D9/00, H03D11/00 take precedence) · CPC title

• H03L7/087

  using at least two phase detectors or a frequency and phase detector in the loop · CPC title

• H03B5/124

  the means comprising a voltage dependent capacitance · CPC title

• H03L7/18

  using a frequency divider or counter in the loop (H03L7/20, H03L7/22 take precedence) · CPC title