Polar receiver with reduced amplitude-phase distortion

Patent metadata

Field	Value
Publication number	US-9319052-B2
Application number	US-201414275477-A
Country	US
Kind code	B2
Filing date	May 12, 2014
Priority date	Mar 15, 2013
Publication date	Apr 19, 2016
Grant date	Apr 19, 2016

Abstract

A receiver includes a harmonic injection-locked oscillator, which receives an RF modulated signal and provides an output to two parallel signal paths. A fundamental injection-locked oscillator is provided on one of the signal paths. A phase discriminator detects a phase difference between signals that have passed through the first and second signal paths. At least one of the signal paths includes an amplitude limiting circuit. One or more of the signal paths may include an adjustable delay circuit.

First claim

We claim:

1. An apparatus comprising:
a harmonic ILO operative to receive an RF modulated signal input and to provide a phase-compressed divided-frequency signal output;
a phase discriminator having a first discriminator input and a second discriminator input, the phase discriminator being operative to provide a phase-detection output representative of a phase difference between a first signal at the first discriminator input and a second signal at the second discriminator input;
a first signal path between the phase-compressed divided-frequency signal output and the first discriminator input;
a fundamental ILO connected on the first signal path, the fundamental ILO being operative to receive the phase-compressed divided-frequency signal output and to provide a phase-locking signal output;
a second signal path between the phase-compressed divided-frequency signal output and the second discriminator input; and
an amplitude limiting circuit on at least one of the first and the second signal paths.

2. The apparatus of claim 1 , wherein the amplitude limiting circuit is connected to the output of the harmonic ILO.

3. The apparatus of claim 1 , wherein the amplitude limiting circuit is connected to the output of the fundamental ILO.

4. The apparatus of claim 1 , wherein the amplitude limiting circuit is located on the second signal path.

5. The apparatus of claim 4 , further comprising an adjustable delay circuit on the first signal path between the harmonic ILO and the fundamental ILO.

6. The apparatus of claim 1 , wherein the amplitude limiting circuit comprises a high-gain saturating amplifier.

7. The apparatus of claim 1 , wherein the phase discriminator is a mixer and a low-pass filter.

8. The method of claim 1 , wherein the harmonic ILO is a second-harmonic ILO.

9. A method comprising:
injecting an RF modulated signal into a harmonic ILO to provide a phase-compressed divided-frequency signal output;
providing the phase-compressed divided-frequency signal output on a first signal path to a first input of a phase discriminator and on a second signal path to a second input of the phase discriminator;
operating an amplitude limiting circuit to limit the amplitude of the phase-compressed divided-frequency signal on at least one of the first signal path and the second signal path;
injecting the phase-compressed divided-frequency signal into a fundamental ILO on the first signal path;
providing an output of the fundamental ILO to the first input of a phase discriminator; and
operating the phase discriminator to provide a phase-detection output representative of a phase difference between a first signal at the first input and a second signal at the second input.

10. The method of claim 9 , wherein the amplitude limiting circuit is on the first signal path.

11. The method of claim 9 , wherein the amplitude limiting circuit is on the second signal path.

12. The method of claim 9 , further comprising adjusting a delay along at least one of the first and the second signal paths.

13. The method of claim 9 , further comprising adjusting a resonance frequency of the fundamental ILO to change the free-running frequency of the fundamental ILO.

14. The method of claim 9 , further comprising adjusting one or more parameters of the harmonic ILO, wherein the one or more parameters include a parameter selected from the group consisting of an injection coefficient, a quality factor, and a resonance frequency of the ILO.

15. An apparatus comprising:
an injection-locked frequency divider having a divider input and a divider output, wherein the divider output produces a phase-compressed divided-frequency signal with respect to a signal received at the divider input;
a phase discriminator having a first discriminator input, a second discriminator input, and a discriminator output;
a first signal path between the divider output and the first discriminator input;
an amplitude limiting circuit on the first signal path;
a second signal path between the divider output and the second discriminator input; and
a fundamental ILO on at least one of the first and second signal paths.

16. The apparatus of claim 15 , wherein the fundamental ILO is on the second signal path.

17. The apparatus of claim 15 , wherein the fundamental ILO is on the first signal path between the amplitude limiting circuit and the first discriminator input.

18. The apparatus of claim 15 , further comprising an adjustable-delay circuit on the second signal path.

19. The apparatus of claim 15 , wherein the amplitude limiting circuit includes at least one inverter circuit.

20. The apparatus of claim 15 , wherein the amplitude limiting circuit comprises a high-gain saturating amplifier.

Assignees

• Innophase Inc

Inventors

• Xu Yang
• Munoz Hermoso Sara

Classifications

• H03L7/085

  concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal (H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00) · CPC title

• H04L27/227

  using coherent demodulation · CPC title

• H04L27/2272 Primary

  using phase locked loops (H04L27/2273 takes precedence) · CPC title

• H03B5/1228

  the amplifier comprising one or more field effect transistors · CPC title

• H03L7/099 Primary

  concerning mainly the controlled oscillator of the loop · CPC title