Opto-electronic device having junction field-effect transistor structure and method of manufacturing the same

US11670665B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11670665-B2
Application numberUS-202016919328-A
CountryUS
Kind codeB2
Filing dateJul 2, 2020
Priority dateFeb 6, 2020
Publication dateJun 6, 2023
Grant dateJun 6, 2023

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Provided are opto-electronic devices with low dark noise and high signal-to-noise ratio and methods of manufacturing the same. An opto-electronic device may include: a semiconductor substrate; a light receiving unit formed in the semiconductor substrate; and a driving circuit arranged on a surface of the semiconductor substrate. The light receiving unit may include: a first semiconductor layer partially arranged in an upper region of the semiconductor substrate and doped with a first conductivity type impurity; a second semiconductor layer arranged on the first semiconductor layer and doped with a second conductivity type impurity; a transparent matrix layer arranged on an upper surface of the second semiconductor layer; a plurality of quantum dots arranged to contact the transparent matrix layer; and a first electrode and a second electrode electrically connected to the second semiconductor layer and respectively arranged on both sides of the transparent matrix layer.

First claim

Opening claim text (preview).

What is claimed is: 1. An opto-electronic device comprising: a semiconductor substrate; a light receiving unit formed in the semiconductor substrate; and a driving circuit arranged on a surface of the semiconductor substrate at a portion of the semiconductor substrate not overlapping the light receiving unit in a plan view, wherein the light receiving unit comprises: a first semiconductor layer arranged in an upper region of the semiconductor substrate and doped with a first conductivity type impurity; a second semiconductor layer arranged on the first semiconductor layer and doped with a second conductivity type impurity different from the first conductivity type impurity; a transparent matrix layer arranged on an upper surface of the second semiconductor layer; a plurality of quantum dots arranged to contact the transparent matrix layer; and a first electrode arranged on a first side of the transparent matrix layer and a second electrode arranged on a second side of the transparent matrix layer opposite to the first side, wherein the first electrode and the second electrode are electrically connected to the second semiconductor layer, wherein the first semiconductor layer is doped to have a first doping concentration and the second semiconductor layer is doped to have a second doping concentration less than the first doping concentration. 2. The opto-electronic device of claim 1 , wherein the plurality of quantum dots are arranged on the upper surface of the second semiconductor layer to be in contact the upper surface of the second semiconductor layer, and the transparent matrix layer is arranged to cover the plurality of quantum dots. 3. The opto-electronic device of claim 1 , wherein the plurality of quantum dots are embedded inside the transparent matrix layer so as not to contact the upper surface of the second semiconductor layer. 4. The opto-electronic device of claim 1 , wherein the transparent matrix layer comprises a transparent oxide semiconductor material. 5. The opto-electronic device of claim 4 , wherein the transparent oxide semiconductor material comprises at least one material selected from silicon indium zinc oxide (SIZO), silicon zinc tin oxide (SZTO), indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), zinc tin oxide (ZTO), CuAlO 2 , CuG 2 O 2 , SrCu 2 O 2 , or SnO 2 . 6. The opto-electronic device of claim 1 , wherein the driving circuit comprises: a plurality of metal layers; and a dielectric layer interposed between the plurality of metal layers.

Assignees

Inventors

Classifications

  • Manufacture or treatment of image sensors covered by group H10F39/12 · CPC title

  • H10F39/196Primary

    Junction field effect transistor [JFET] image sensors; Static induction transistor [SIT] image sensors · CPC title

  • Quantum dots · CPC title

  • the integrated elements comprising a transistor · CPC title

  • Photosensitive area · CPC title

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What does patent US11670665B2 cover?
Provided are opto-electronic devices with low dark noise and high signal-to-noise ratio and methods of manufacturing the same. An opto-electronic device may include: a semiconductor substrate; a light receiving unit formed in the semiconductor substrate; and a driving circuit arranged on a surface of the semiconductor substrate. The light receiving unit may include: a first semiconductor layer …
Who is the assignee on this patent?
Samsung Electronics Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10F39/196. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jun 06 2023 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 6 related publications on this page (citations in our corpus or others sharing the same primary CPC).