3D buildup of thermally conductive layers to resolve die height differences

Patent metadata

Field	Value
Publication number	US-11670561-B2
Application number	US-201916721802-A
Country	US
Kind code	B2
Filing date	Dec 19, 2019
Priority date	Dec 19, 2019
Publication date	Jun 6, 2023
Grant date	Jun 6, 2023

Abstract

Embodiments include semiconductor packages and a method to form such packages. A semiconductor package includes first, second, and third microelectronic devices on a package substrate. The first microelectronic device has a top surface substantially coplanar to a top surface of the second microelectronic device. The third microelectronic device has a top surface above the top surfaces of the first and second microelectronic devices. The semiconductor package includes a first conductive layer on the first and second microelectronic devices, and a second conductive layer on the third microelectronic device. The second conductive layer has a thickness less than a thickness of the first conductive layer, and a top surface substantially coplanar to a top surface of the first conductive layer. The semiconductor includes thermal interface materials on the first and second conductive layers. The first and second conductive layers are comprised of copper, silver, boron nitride, or graphene.

First claim

What is claimed is:

1. A semiconductor package, comprising:
a first microelectronic device and a second microelectronic device on a package substrate, wherein the first microelectronic device has a top surface that is substantially coplanar to a top surface of the second microelectronic device;
a third microelectronic device on the package substrate, wherein the third microelectronic device has a top surface positioned above the top surfaces of the first and second microelectronic devices;
a first conductive layer on the first and second microelectronic devices;
a second conductive layer on the third microelectronic device, wherein the second conductive layer has a thickness that is less than a thickness of the first conductive layer, and wherein the second conductive layer has a top surface that is substantially coplanar to a top surface of the first conductive layer; and
a first thermal interface material (TIM) on the first conductive layer, and a second TIM on the second conductive layer.

2. The semiconductor package of claim 1 , wherein the first and second conductive layers are comprised of copper, silver, boron nitride, or graphene.

3. The semiconductor package of claim 1 , wherein the first microelectronic device is adjacent to the second microelectronic device, and wherein the third microelectronic device is adjacent to the second microelectronic device.

4. The semiconductor package of claim 1 , wherein the first microelectronic device includes a plurality of first top dies on a first bottom die, wherein the second microelectronic device includes a plurality of second top dies on a second bottom die, and wherein the third microelectronic device is comprised of a die, a stack of dies, a high bandwidth memory (HBM) die, or a stack of HBM dies.

5. The semiconductor package of claim 1 , wherein the first TIM is directly on the top surface of the first conductive layer, wherein the second TIM is directly on the top surface of the second conductive layer, wherein the first TIM has a thickness that is substantially equal to a thickness of the second TIM, wherein the first conductive layer has a width that is equal to or greater than a width of the first and second microelectronic devices, and wherein the second conductive layer has a width that is equal to a width of the third microelectronic device.

6. The semiconductor package of claim 4 , further comprising:
an encapsulation layer on a top surface of the first bottom die and a top surface of the second bottom die, wherein the encapsulation layer has a top surface that is substantially coplanar to top surfaces of the plurality of first and second top dies, wherein the first conductive layer is directly on the top surfaces of the encapsulation layer and the plurality of first and second top dies, and wherein the second conductive layer is directly on the top surface of the third microelectronic device;
a plurality of bridges in the package substrate, wherein the plurality of bridges communicatively couple the first, second, and third microelectronic devices;
an adhesive layer directly couples the first and second microelectronic devices onto the package substrate;
a plurality of solder balls directly couple the third microelectronic device onto the package substrate;
a plurality of interconnects in the first and second bottom dies; and
an integrated heat spreader (IHS) directly on a top surface of the first TIM and a top surface of the second TIM, wherein the first TIM is positioned directly between the first conductive layer and the IHS, and wherein the second TIM is positioned directly between the second conductive layer and the IHS.

7. The semiconductor package of claim 1 , wherein the first conductive layer is comprised of a shared first conductive layer or a separated first conductive layer, wherein the shared first conductive layer covers both the first and second microelectronic devices, or the separated first conductive layer has a first portion that only covers the first microelectronic device, and a second portion that only covers the second microelectronic device, wherein the first TIM is comprised of a shared first TIM or a separated first TIM, and wherein the shared first TIM covers both the first and second microelectronic devices, or the separated first TIM has a first portion that only covers the first microelectronic device, and a second portion that only covers the second microelectronic device.

8. The semiconductor package of claim 1 , wherein the third microelectronic device has a thickness that is greater than a thickness of the first and second microelectronic devices.

9. The semiconductor package of claim 1 , further comprising a plurality of conductive slugs coupled to a periphery region of a bottom surface of the first conductive layer, wherein the plurality of conductive slugs are comprised of one or more different shapes, and wherein the one or more different shapes of the plurality of conductive slugs include rectangular conductive slugs, L-shaped conductive slugs, Z-shaped conductive slugs, circular conductive slugs, or trapezoidal conductive slugs.

10. A semiconductor package, comprising:
a first microelectronic device and a second microelectronic device on a package substrate, wherein the first microelectronic device has a top surface that is substantially coplanar to a top surface of the second microelectronic device;
a third microelectronic device on the package substrate;
a first conductive layer on the first and second microelectronic devices;
a second conductive layer on the third microelectronic device, wherein the second conductive layer has a thickness that is different than a thickness of the first conductive layer, and wherein the second conductive layer has a top surface that is substantially coplanar to a top surface of the first conductive layer;
a first thermal interface material (TIM) on the first conductive layer, and a second TIM on the second conductive layer, wherein the first TIM has a thickness that is substantially equal to a thickness of the second TIM;
an integrated heat spreader (IHS) on the first and second TIMs; and
a plurality of conductive slugs coupled to a periphery region of a bottom surface of the first conductive layer.

11. The semiconductor package of claim 10 , wherein the first and second conductive layers and the plurality of conductive slugs are comprised of copper, silver, boron nitride, or graphene, and wherein the thickness of the second conductive layer is greater or less than a thickness of the first conductive layer.

12. The semiconductor package of claim 10 , wherein the first microelectronic device is adjacent to the second microelectronic device, and wherein the third microelectronic device is adjacent to the second microelectronic device.

13. The semiconductor package of claim 10 , wherein the first microelectronic device includes a plurality of first top dies on a first bottom die, wherein the second microelectronic device includes a plurality of second top dies on a second bottom die, wherein the third microelectronic device is comprised of a die, a stack of dies, a high bandwidth memory (HBM) die, or a stack of HBM dies, and wherein the third microelectronic device has a top surface positioned above or below the top surfaces of the first and second microelectronic devices.

14. The semiconductor package of claim 10 , wherein the first TIM is directly on the top surface of the first conductive layer, wherein the second TIM is directly on the top surface of the second conductive layer, wherein the first conductive layer has a width that is equal to or greater than a width of the first and second mic

Assignees

• Intel Corp

Inventors

• Wan Zhimin
• JHA Chandra Mohan
• Chang Je-Young
• Chiu Chia-Pin
• Wang Liwei

Classifications

• H10W70/618

  the bridge chips being embedded in the package substrates, interposers or redistribution layers · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W74/131

  the semiconductor body being only partially enclosed · CPC title

• H10W74/01

  Manufacture or treatment · CPC title

• H10W70/611

  for connecting multiple chips together · CPC title