Accelerator controlling memory device, computing system including accelerator, and operating method of accelerator

Patent metadata

Field	Value
Publication number	US-11670355-B2
Application number	US-202117406511-A
Country	US
Kind code	B2
Filing date	Aug 19, 2021
Priority date	Jan 6, 2021
Publication date	Jun 6, 2023
Grant date	Jun 6, 2023

Abstract

Provided are an accelerator controlling a memory device, a computing system including the accelerator, and an operating method of the accelerator. The accelerator includes: a signal control/monitoring circuit configured to detect an entry to a self-refresh mode of a memory device and an exit from the self-refresh mode based on monitoring a signal provided from a host; an accelerator logic configured to generate a first command/address signal and a first piece of data; and a selector configured to output the first command/address signal and the first piece of data to the memory device based on detection of the entry to the self-refresh mode, and output a second command/address signal and a second piece of data provided from the host, to the memory device, based on detection of the exit from the self-refresh mode.

First claim

What is claimed is:

1. An accelerator comprising:
a signal control/monitoring circuit configured to detect an entry to a self-refresh mode of a memory device and an exit from the self-refresh mode based on monitoring a signal provided from a host;
an accelerator logic configured to generate a first command/address signal and a first piece of data; and
a selector configured to output the first command/address signal and the first piece of data to the memory device based on detection of the entry to the self-refresh mode, and output a second command/address signal and a second piece of data provided from the host to the memory device, based on detection of the exit from the self-refresh mode.

2. The accelerator of claim 1 , wherein the signal control/monitoring circuit is further configured to output a mode select signal for controlling the selector, based on the detection of the entry to the self-refresh mode and the exit from the self-refresh mode.

3. The accelerator of claim 1 , wherein the signal control/monitoring circuit is further configured to detect the entry to the self-refresh mode based on the signal provided from the host indicating a self-refresh command.

4. The accelerator of claim 1 , wherein the signal provided from the host includes a chip select signal, and the signal control/monitoring circuit is further configured to detect the exit from the self-refresh mode by monitoring a change of a logic state of the chip select signal.

5. The accelerator of claim 4 , wherein the chip select signal has a wave form defined by a double data rate 5 (DDR5) specification, and
the signal control/monitoring circuit is further configured to detect the exit from the self-refresh mode based on a change of the logic state of the chip select signal from a first logic state to a second logic state.

6. The accelerator of claim 5 , wherein an access to the memory device by the accelerator is stopped at a time point at which the logic state of the chip select signal is changed to the second logic state.

7. The accelerator of claim 5 , wherein the logic state of the chip select signal is maintained in the second logic state during a first interval and then is changed to the first logic state, and
an access to the memory device by the accelerator is maintained in at least a portion of the first interval.

8. The accelerator of claim 1 , further comprising a clock generator configured to generate a clock signal based on control by the signal control/monitoring circuit,
wherein the clock generator is further configured to activate and output the clock signal to the memory device while the accelerator accesses the memory device.

9. The accelerator of claim 8 , wherein the clock generator is further configured to activate the clock signal based on detection of the entry to the self-refresh mode, and deactivate the clock signal based on detection of the exit from the self-refresh mode.

10. The accelerator of claim 1 , wherein the accelerator is further configured to:
store, in the accelerator logic, data that has been changed while the accelerator accesses the memory device; and
after the exit from the self-refresh mode, provide the changed data to the host.

11. A computing system comprising:
a memory device comprising one or more channels;
a host configured to generate a first command/address signal and a first piece of data, and generate a self-refresh command for controlling the memory device to enter a self-refresh mode; and
an accelerator comprising an accelerator logic configured to generate a second command/address signal and a second piece of data, the accelerator being configured to provide the first command/address signal and the first piece of data to the memory device while the host occupies the memory device, and provide the second command/address signal and the second piece of data, generated by the accelerator logic, to the memory device based on detection of the self-refresh command generated by the host.

12. The computing system of claim 11 , wherein the accelerator further comprises:
a signal control/monitoring circuit configured to generate a mode select signal; and
a selector configured to, according to the mode select signal, provide the first command/address signal and the first piece of data to the memory device, or provide the second command/address signal and the second piece of data to the memory device.

13. The computing system of claim 12 , wherein the host is further configured to generate a chip select signal, and
the signal control/monitoring circuit is further configured to detect an exit from the self-refresh mode by monitoring a change of a logic state of the chip select signal, and control the mode select signal for controlling the selector to provide the first command/address signal and the first piece of data to the memory device based on detection of the exit from the self-refresh mode.

14. The computing system of claim 12 , wherein the memory device comprises a first channel and a second channel individually communicating with the accelerator via independent paths, and
the selector comprises a first selector correspondingly to the first channel, and a second selector correspondingly to the second channel.

15. The computing system of claim 11 , wherein the accelerator further comprises a clock generator configured to generate a clock signal for accessing the memory device, and
based on the detection of the self-refresh command, the clock signal is activated and provided to the memory device.

16. The computing system of claim 11 , wherein the memory device comprises a dual in memory module (DIMM),
the computing system further comprises a printed circuit board (PCB) on which a plurality of DIMM slots are provided, the memory device being mounted on the plurality of DIMM slots, and
the accelerator is mounted on any one of the plurality of DIMM slots.

17. The computing system of claim 11 , wherein the host is further configured to generate a self-refresh exit command for controlling the memory device to exit from the self-refresh mode, and
the accelerator is further configured to, based on detection of the self-refresh exit command from the host, provide the first command/address signal and the first piece of data to the memory device.

18. The computing system of claim 11 , wherein the memory device is configured to communicate with the host and the accelerator based on a double data rate 5 (DDR5) specification.

19. A method of operating an accelerator, the method comprising:
receiving a first command/address signal and a first piece of data generated by a host and transmitting the received first command/address signal and the received first piece of data to a memory device;
detecting an entry to a self-refresh mode of the memory device by monitoring a signal from the host;
generating a first clock signal used for accessing the memory device, based on a result of the detecting; and
accessing to the memory device by providing, to the memory device, the first clock signal, a second command/address signal, and a second piece of data, the second command/address signal and the second piece of data being generated by the accelerator.

20. The method of claim 19 , further comprising:
detecting an exit from the self-refresh mode of the memory device by monitoring the signal from the host;
based on detection of the exit from the self-refresh mode, deactivating generation of the first clock signal; and
transmitting to the memory device the first command/address signal and

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Minsu
• Kim Namhyung
• Kim Daejeong
• Kim Dohan
• Park Chanik
• Seo Deokho
• Shin Wonjae
• Lee Changmin
• Jung Ilguy
• CHOI Insu

Classifications

• G06F13/1668 Primary

  Details of memory controller · CPC title

• G11C11/40611

  External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh · CPC title

• G06F13/1636 Primary

  using refresh · CPC title

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title

• G11C11/4096

  Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches · CPC title