Cascode amplifier bias circuits

Patent metadata

Field	Value
Publication number	US-11664769-B2
Application number	US-202217843372-A
Country	US
Kind code	B2
Filing date	Jun 17, 2022
Priority date	Sep 16, 2016
Publication date	May 30, 2023
Grant date	May 30, 2023

Abstract

Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.

First claim

What is claimed is:

1. A method for biasing the final stages of a cascode amplifier, including:
(a) providing a cascode amplifier having at least two serially connected field effect transistor (FET) stages, each FET stage having a gate, a drain, and a source, the bottom FET stage having an input configured to be coupled to an RF input signal to be amplified, and the top FET stage of the cascode amplifier having an output for providing an amplified RF input signal;
(b) providing a cascode reference circuit having at least two serially connected FET stages, each FET having a gate, a drain, and a source, the gates of the bottom two FET stages of the cascode reference circuit being coupled to the corresponding gates of the bottom two FET stages of the cascode amplifier, for biasing the cascode amplifier to output a final current approximately equal to a multiple of a mirror current in the cascode reference circuit;
(c) automatically adjusting a gate bias voltage applied to the respective gates of the bottom FET stage of the cascode amplifier and of the cascode reference circuit in response to variations in voltage and/or current in the cascode reference circuit so as to force the mirror current in the cascode reference circuit to be approximately equal to a selected current value; and
(d) coupling a respective decoupling network between corresponding gates of each of the bottom two FET stages of the cascode amplifier, wherein at least one decoupling network includes a programmable resistance element for varying bias levels to the coupled gates.

2. The method of claim 1 , wherein the cascode reference circuit is a split cascode reference circuit.

3. The method of claim 1 , further including coupling an input impedance matching network to the input of the bottom FET stage, the input impedance matching network configured to be coupled to the RF input signal to be amplified.

4. The method of claim 1 , further including coupling an output impedance matching network to the output.

5. The method of claim 1 , wherein at least one decoupling network includes a programmable resistance element for varying bias levels to the coupled gates.

6. The method of claim 1 , further including:
(a) coupling a degeneration inductor between the source of the bottom FET stage of the cascode amplifier and RF ground, the degeneration inductor having a resistance Rdeg; and
(b) coupling a compensation resistor between the source of the bottom FET stage of the cascode reference circuit and RF ground, the compensation resistor having a resistance Rcomp such that the voltage at the source of the bottom FET stage of the cascode reference circuit closely approximates the voltage at the source of the bottom FET stage of the cascode amplifier.

7. A method for biasing the final stages of a cascode amplifier, including:
(a) providing a cascode amplifier having at least two serially connected field effect transistor (FET) stages, each FET stage having a gate, a drain, and a source, the bottom FET stage having an input configured to be coupled to an RF input signal to be amplified, and the top FET stage of the cascode amplifier having an output for providing an amplified RF input signal;
(b) providing a cascode reference circuit having at least two serially connected FET stages, each FET having a gate, a drain, and a source, the gates of the bottom two FET stages of the cascode reference circuit being coupled to the corresponding gates of the bottom two FET stages of the cascode amplifier, for biasing the cascode amplifier to output a final current approximately equal to a multiple of a mirror current in the cascode reference circuit; and
(c) coupling a current source to the drain of the top FET stage of the cascode reference circuit and to the respective gates of the bottom FET stages of the cascode reference circuit and the cascode amplifier; and
(d) coupling a respective decoupling network between corresponding gates of each of the bottom two FET stages of the cascode amplifier, wherein at least one decoupling network includes a programmable resistance element for varying bias levels to the coupled gates;

wherein the respective gates of the bottom FET stages of the cascode reference circuit and the cascode amplifier are responsive to variations in voltage in the cascode reference circuit such that the mirror current in the cascode reference circuit is forced to be approximately equal to a selected current value.

8. The method of claim 7 , wherein the cascode reference circuit is a split cascode reference circuit.

9. The method of claim 7 , further including coupling an input impedance matching network to the input of the bottom FET stage, the input impedance matching network configured to be coupled to the RF input signal to be amplified.

10. The method of claim 7 , further including coupling an output impedance matching network to the output.

11. The method of claim 7 , wherein at least one decoupling network includes a programmable resistance element for varying bias levels to the coupled gates.

12. The method of claim 7 , further including:
(a) coupling a degeneration inductor between the source of the bottom FET stage of the cascode amplifier and RF ground, the degeneration inductor having a resistance Rdeg; and
(b) coupling a compensation resistor between the source of the bottom FET stage of the cascode reference circuit and RF ground, the compensation resistor having a resistance Rcomp such that the voltage at the source of the bottom FET stage of the cascode reference circuit closely approximates the voltage at the source of the bottom FET stage of the cascode amplifier.

13. A method for biasing the final stages of a cascode amplifier, including:
(a) providing a cascode amplifier having at least two serially connected field effect transistor (FET) stages, each FET stage having a gate, a drain, and a source, the bottom FET stage having an input configured to be coupled to an RF input signal to be amplified, and the top FET stage of the cascode amplifier having an output for providing an amplified RF input signal;
(b) providing a cascode reference circuit having at least two serially connected FET stages, each FET having a gate, a drain, and a source, the gates of the bottom two FET stages of the cascode reference circuit being coupled to the corresponding gates of the bottom two FET stages of the cascode amplifier, for biasing the cascode amplifier to output a final current approximately equal to a multiple of a mirror current in the cascode reference circuit;
(c) coupling a current source to the drain of the top FET stage of the cascode reference circuit;
(d) providing a source follower FET having a gate, a drain, and a source, the drain of the source follower FET being coupled to a voltage source, the gate of the source follower FET being coupled to the drain of the top FET stage of the cascode reference circuit, and the source of the source follower FET being coupled to a bias current source and to the gates of the bottom FET stages of the cascode reference circuit and the cascode amplifier, the source follower FET being responsive to variations in voltage and/or current in the cascode reference circuit to output an adjustment gate bias voltage applied to the respective gates of the bottom FET stage of the cascode amplifier and of the cascode reference circuit that forces the mirror current in the cascode reference circuit to be approximately equal to a selected current value; and
(e) coupling a respective decoupling network between corresponding gates of each of the bottom two FET stages of the cascode amplifier, wherein at least one decoupling network includes a programmabl

Assignees

• Psemi Corp

Inventors

• Klaren Jonathan James
• Kovac David
• Shapiro Eric S
• Murphy Christopher C
• Englekirk Robert Mark
• Bargroff Keith
• Ranta Tero Tapio

Classifications

• H03F2200/78

  A comparator being used in a controlling circuit of an amplifier · CPC title

• H03F2200/21

  Bias resistors are added at the input of an amplifier · CPC title

• H03F3/245

  with semiconductor devices only · CPC title

• H03F2200/301

  the loading circuit of an amplifying stage comprising a coil · CPC title

• H03F2200/102

  A non-specified detector of a signal envelope being used in an amplifying circuit · CPC title