Semiconductor device, power module and method for manufacturing the semiconductor device

Patent metadata

Field	Value
Publication number	US-11664466-B2
Application number	US-201817263617-A
Country	US
Kind code	B2
Filing date	Aug 1, 2018
Priority date	Aug 1, 2018
Publication date	May 30, 2023
Grant date	May 30, 2023

Abstract

A semiconductor device includes: a conductive semiconductor substrate in which a trench is formed on the first main surface; a plurality of conductive layers, each of which is either a first conductive layer or a second conductive layer, which are laminated on one another along a surface normal direction of a side surface of the trench; and dielectric layers arranged between a conductive layer closest to the side surface of the trench among the plurality of conductive layers and the side surface of the trench, and between the plurality of corresponding conductive layers. The first conductive layer is electrically insulated from the semiconductor substrate, and the semiconductor substrate that electrically connects to the second conductive layer inside the trench electrically connects to the second electrode.

First claim

The invention claimed is:

1. A semiconductor device comprising:
a semiconductor substrate having first and second main surfaces facing each other, in which a trench is formed on the first main surface, wherein an entirety of the semiconductor substrate is conductive;
a plurality of conductive layers, each of which is either a first conductive layer or a second conductive layer, the conductive layers being laminated on one another along a side surface of the trench in a direction that is normal to the side surface of the trench;
dielectric layers arranged between a conductive layer closest to the side surface of the trench among the plurality of conductive layers and the side surface of the trench, and between the plurality of corresponding conductive layers;
a first electrode that is arranged outside the trench and electrically connects to the first conductive layer outside the trench in plan view, the first electrode physically contacting the first conductive layer; and
a second electrode that is arranged on the second main surface of the semiconductor substrate and electrically connects to the second conductive layer via the semiconductor substrate,
wherein the first conductive layer is electrically insulated from the semiconductor substrate,
wherein the semiconductor substrate that electrically connects to the second conductive layer inside the trench electrically connects to the second electrode, and
wherein the first conductive layer includes one first conductive layer and another first conductive layer, the first electrode extending only through the one first conductive layer, of the first conductive layer, in a contact hole, the contact hole being laterally adjacent the trench in plan view.

2. The semiconductor device according to claim 1 , wherein the trench is embedded with a laminated structure of the plurality of conductive layers and the dielectric layers.

3. The semiconductor device according to claim 1 , wherein four or more conductive layers including the first conductive layer and the second conductive layer are provided.

4. The semiconductor device according to claim 1 ,
wherein the conductive layer closest to the side surface of the trench among the plurality of conductive layers is defined as a first conductive layer,
wherein odd number-th conductive layers in the plurality of conductive layers electrically connect to one another, and
wherein even number-th conductive layers in the plurality of conductive layers electrically connect to one another.

5. The semiconductor device according to claim 1 , wherein the dielectric layers have a structure in which a plurality of dielectric films made of materials different from one another are laminated on one another.

6. The semiconductor device according to claim 1 , further comprising a cooling device disposed so as to face at least either the first main surface of the semiconductor substrate or the second main surface of the semiconductor substrate.

7. The semiconductor device according to claim 1 , wherein the semiconductor substrate is a single crystal silicon substrate.

8. The semiconductor device according to claim 1 , wherein the semiconductor substrate is a polycrystalline silicon substrate.

9. The semiconductor device according to claim 1 , wherein the dielectric layers include at least either silicon oxide films or silicon nitride films.

10. A power module comprising:
the semiconductor device according to claim 1 ,
a first power semiconductor element in which a drain electrode connects to the second electrode; and
a second power semiconductor element in which a source electrode connects to the first electrode,
wherein a source electrode of the first power semiconductor element and a drain electrode of the second power semiconductor element electrically connect to each other.

Assignees

• Nissan Motor
• Renault Sas

Inventors

• Marui Toshiharu
• Hayashi Tetsuya
• Numakura Keiichiro
• Ni Wei
• Tanaka Ryota

Classifications

• H10W90/00

  Package configurations · CPC title

• H10D1/716

  having vertical extensions · CPC title

• H10D1/047

  of conductor-insulator-semiconductor capacitors, e.g. trench capacitors · CPC title

• H10D1/042 Primary

  using deposition processes to form electrode extensions · CPC title

• H10D1/665 Primary

  Trench conductor-insulator-semiconductor capacitors, e.g. trench MOS capacitors · CPC title