LDMOS architecture and method for forming

Patent metadata

Field	Value
Publication number	US-11664449-B2
Application number	US-202217653300-A
Country	US
Kind code	B2
Filing date	Mar 3, 2022
Priority date	May 20, 2020
Publication date	May 30, 2023
Grant date	May 30, 2023

Abstract

A method for forming a semiconductor device involves providing a semiconductor wafer having an active layer of a first conductivity type. First and second gates having first and second gate polysilicon are formed on the active layer. A first mask region is formed on the active layer. Between the first and second gates, using the first mask region, the first gate polysilicon, and the second gate polysilicon as a mask, a deep well of a second conductivity type, a shallow well of the second conductivity type, a source region of the first conductivity type, and first and second channel regions of the second conductivity type, are formed. In the active layer, using one or more second mask regions, first and second drift regions of the first conductivity type, first and second drain regions of the first conductivity type, and a source connection region of the second conductivity type, are formed.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a semiconductor wafer having an active layer of a first conductivity type, the active layer comprising a deep well of a second conductivity type, a shallow well of the second conductivity type, a source region of the first conductivity type, a first channel region of the second conductivity type, a second channel region of the second conductivity type, a first drift region of the first conductivity type, a second drift region of the first conductivity type, a first drain region of the first conductivity type, a second drain region of the first conductivity type, and a source connection region of the second conductivity type;
first gate polysilicon formed above the active layer and having a first polysilicon gate spacer laterally disposed next to the first gate polysilicon;
second gate polysilicon formed above the active layer and having a second polysilicon gate spacer laterally disposed next to the second gate polysilicon, the source connection region being laterally disposed between the first polysilicon gate spacer and the second polysilicon gate spacer;
a first gate shield formed above the first gate polysilicon;
a second gate shield formed above the second gate polysilicon;
a dielectric region formed over the active layer; and
a metal source contact extending vertically from a top surface of the dielectric region to the source connection region, the metal source contact being laterally disposed between the first polysilicon gate spacer and the second polysilicon gate spacer.

2. The semiconductor device of claim 1 , wherein:
the first conductivity type is an n-type conductivity; and
the second conductivity type is a p-type conductivity.

3. A method for forming a semiconductor device, comprising:
providing a semiconductor wafer having a substrate layer, and an active layer of a first conductivity type;
forming a first gate on the active layer, the first gate comprising first gate polysilicon;
forming a second gate on the active layer, the second gate being laterally disposed from the first gate and comprising second gate polysilicon;
forming in the active layer between the first gate and the second gate using a lateral extent of the first gate polysilicon and a lateral extent of the second gate polysilicon as a mask, a deep well of a second conductivity type, a shallow well of the second conductivity type, a source region of the first conductivity type, and a channel region segmented into a first channel region of the second conductivity type, and a second channel region of the second conductivity type; and
forming in the active layer using one or more mask regions, a first drift region of the first conductivity type, a second drift region of the first conductivity type, a first drain region of the first conductivity type, a second drain region of the first conductivity type, and a source connection region of the second conductivity type.

4. The method of claim 3 , wherein:
the lateral extent of the first gate polysilicon and the lateral extent of the second gate polysilicon shield the active layer from dopants implanted at an implantation angle that is perpendicular to a horizontal plane of the active layer, the horizontal plane being parallel to a top surface of the active layer.

5. The method of claim 4 , wherein:
forming the first channel region comprises implanting and thermally driving dopants of the second conductivity type at a first range of implantation angles such that the dopants of the second conductivity type extend under the first gate polysilicon for a first lateral extent, the lateral extents of the first and second gate polysilicon being used as a mask; and
forming the second channel region comprises implanting and thermally driving the dopants of the second conductivity type at a second range of implantation angles such that the dopants of the second conductivity type extend under the second gate polysilicon for a second lateral extent, the lateral extents of the first and second gate polysilicon being used as a mask.

6. The method of claim 4 , wherein forming the shallow well comprises:
implanting dopants of the second conductivity type at an implantation angle such that the shallow well has a lateral extent that is laterally aligned with an inner edge of the first gate polysilicon and an inner edge of the second gate polysilicon, the lateral extents of the first and second gate polysilicon being used as a mask.

7. The method of claim 4 , wherein forming the deep well comprises:
implanting dopants of the second conductivity type at an implantation angle such that the deep well is formed directly below the source region, the lateral extents of the first and second gate polysilicon being used as a mask.

8. The method of claim 4 , wherein forming the source region comprises:
implanting dopants of the first conductivity type at an implantation angle such that the source region is laterally aligned with an inner edge of the first gate polysilicon and an inner edge of the second gate polysilicon, the lateral extents of the first and second gate polysilicon being used as a mask.

9. The method of claim 3 , wherein forming the first drift region and the second drift region comprises:
forming a drift region mask on the active layer; and
implanting dopants of the first conductivity type at an implantation angle such that the first drift region and the second drift region are each laterally aligned with a respective edge of the drift region mask.

10. The method of claim 3 , wherein forming the first drain region and the second drain region comprises:
forming a drain region mask on the active layer; and
implanting dopants of the first conductivity type at an implantation angle such that the first drain region and the second drain region are each laterally aligned with a respective edge of the drain region mask.

11. The method of claim 3 , wherein before the forming of the source connection region, the method further comprises:
forming a first polysilicon gate spacer on the active layer and laterally disposed next to an inner edge of the first gate polysilicon and vertically disposed above the source region; and
forming a second polysilicon gate spacer on the active layer and laterally disposed next to an inner edge of the second gate polysilicon and vertically disposed above the source region.

12. The method of claim 11 , wherein forming the source connection region comprises:
forming a first region of photoresist on the active layer, on the first gate polysilicon, and on a first lateral extent of the first polysilicon gate spacer, the first region of photoresist excluding a first lateral extent of the active layer disposed between the first polysilicon gate spacer and the second polysilicon gate spacer;
forming a second region of photoresist on the active layer, on the second gate polysilicon, and on a first lateral extent of the second polysilicon gate spacer, the second region of photoresist excluding the first lateral extent of the active layer disposed between the first polysilicon gate spacer and the second polysilicon gate spacer; and
implanting dopants of the second conductivity type in the first lateral extent of the active layer disposed between the first polysilicon gate spacer and the second polysilicon gate spacer.

13. The method of claim 12 , wherein:
the first lateral extent of the first polysilicon gate spacer is an entire lateral extent of the first polysilicon gate spacer, and the first region of photoresist is formed on the active layer and extends beyond the first polysilicon gate spacer for a second lateral extent of the active la

Assignees

• Silanna Asia Pte Ltd

Inventors

• Snyder David
• Tu Shanghui Larry

Classifications

• H10P32/1406

  by ion implantation · CPC title

• H10P32/171

  being group IV material · CPC title

• H10P30/222

  characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221) · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/22

  using masks · CPC title