Staggered lines for interconnect performance improvement and processes for forming such

Patent metadata

Field	Value
Publication number	US-11664305-B2
Application number	US-201916455662-A
Country	US
Kind code	B2
Filing date	Jun 27, 2019
Priority date	Jun 27, 2019
Publication date	May 30, 2023
Grant date	May 30, 2023

Abstract

An interconnect structure is disclosed. The interconnect structure includes a first line of interconnects and a second line of interconnects. The first line of interconnects and the second line of interconnects are staggered. The individual interconnects of the second line of interconnects are laterally offset from individual interconnects of the first line of interconnects. A dielectric material is adjacent to at least a portion of the individual interconnects of at least one of the first line of interconnects and the second line of interconnects.

First claim

What is claimed is:

1. An interconnect structure, comprising:
a first line of interconnects;
a second line of interconnects, the first line of interconnects and the second line of interconnects are staggered, wherein individual interconnects of the second line of interconnects are laterally offset from individual interconnects of the first line of interconnects; and
a dielectric material adjacent to at least a portion of the individual interconnects of at least one of the first line of interconnects and the second line of interconnects.

2. The interconnect structure of claim 1 , further comprising air-gaps between the individual interconnects of the first line of interconnects.

3. The interconnect structure of claim 1 , further comprising air-gaps between the individual interconnects of the second line of interconnects.

4. The interconnect structure of claim 1 , wherein both the first line of interconnects and the second line of interconnects includes air-gaps between individual interconnects.

5. The interconnect structure of claim 1 , wherein the first line of interconnects and the second line of interconnects are at least partially surrounded by etch stop.

6. The interconnect structure of claim 1 , further comprising a dielectric layer above the first line of interconnects.

7. An interconnect structure, comprising:
a first line of interconnects;
a second line of interconnects, the first line of interconnects and the second line of interconnects are staggered wherein individual interconnects of the second line of interconnects are laterally offset from the individual interconnects of the first line of interconnects; and
a dielectric material occupies the space between individual interconnects of the first line of interconnects and individual interconnects of the second line of interconnects.

8. The interconnect structure of claim 7 , wherein the first line of interconnects is connected to a metal layer located below the second line of interconnects.

9. The interconnect structure of claim 7 , wherein the second line of interconnects is connected to a metal layer located above the first line of interconnects.

10. The interconnect structure of claim 7 , wherein the first line of interconnects and the second line of interconnects have different patterns.

11. The interconnect structure of claim 7 , wherein the first line of interconnects and the second line of interconnects have different widths and pitches.

12. The interconnect structure of claim 7 , wherein the first line of interconnects and the second line of interconnects have different heights.

13. The interconnect structure of claim 7 , wherein the first line of interconnects and the second line of interconnects overlap vertically.

14. The interconnect structure of claim 7 , wherein at least one interconnect of the first line of interconnects and at least one interconnect of the second line of interconnects together have a T structure.

15. The interconnect structure of claim 7 , further comprising at least one interconnect that is a part of both the first interconnect line and the second interconnect line and extends from the first interconnect line to the second interconnect line.

16. The interconnect structure of claim 7 , wherein a top or bottom portion of at least one of the first line of interconnects and the second line of interconnects is rounded.

17. The interconnect structure of claim 7 , wherein air-gaps extend the entire length of both the first line of interconnects and the second line of interconnects.

18. A system, comprising:
a storage component;
a plurality of integrated circuit die including one or more interconnection structures, the interconnection structures including:
a first line of interconnects;
a second line of interconnects, the first line of interconnects and the second line of interconnects are staggered, wherein individual interconnects of the second line of interconnects are laterally offset from the individual interconnects of the first line of interconnects; and
a dielectric material adjacent to at least a portion of the individual interconnects of at least one of the first line of interconnects and the second line of interconnects.

19. The system of claim 18 , wherein the first line of interconnects includes air-gaps between the individual interconnects of the first line of interconnects and the second line of interconnects includes dielectric material that fully occupies the space between the individual interconnects of the second line of interconnects.

20. The system of claim 18 , wherein the second line of interconnects includes air-gaps between the individual interconnects of the second line of interconnects and the first line of interconnects includes dielectric material that fully occupies the space between the individual interconnects of the second line of interconnects.

Assignees

• Intel Corp

Inventors

• Lin Kevin Lai
• Chandhok Manish
• Reshotko Miriam
• Jezewski Christopher
• Han Eungnak
• Singh Gurpreet
• Atanasov Sarah
• Young Ian A

Classifications

• H10W20/421

  Skip vias, i.e. vias that do not connect all metallization layers that they pass through · CPC title

• H10W20/081

  by forming openings in the dielectric parts · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/47

  comprising two or more dielectric layers having different properties, e.g. different dielectric constants · CPC title