Memory module having volatile and non-volatile memory subsystems and method of operation

Patent metadata

Field	Value
Publication number	US-11663121-B2
Application number	US-202117531743-A
Country	US
Kind code	B2
Filing date	Nov 20, 2021
Priority date	Nov 7, 2013
Publication date	May 30, 2023
Grant date	May 30, 2023

Abstract

A memory module comprises a volatile memory subsystem including DRAM, a non-volatile memory subsystem including Flash memory, and a module control device. The Flash memory includes main Flash providing a main Flash memory space and scratch Flash providing a scratch Flash memory space. The module control device is configured to receive a request from the memory controller to move one or more segments of data in a first Flash block in the main Flash to the DRAM and to, for each respective segment of data: select a respective set of pages in the DRAM; transfer respective data stored in the respective set of pages from the DRAM to a corresponding segment in the scratch Flash; and transfer the respective segment of data to the respective set of pages in the DRAM. Thus, data can be moved segment by segment between the DRAM and the Flash memory.

First claim

We claim:

1. A memory module operable in a computer system, the computer system including a memory controller coupled to the memory module via a memory channel, the memory channel including a data bus and a control/address (C/A) bus, the memory module comprising:
a volatile memory subsystem coupled to the memory channel, the volatile memory subsystem including dynamic random access memory (DRAM);
a non-volatile memory subsystem, the non-volatile memory subsystem including Flash memory, the Flash memory including main Flash providing a main Flash memory space and scratch Flash providing a scratch Flash memory space;
buffer memory;
a module control device coupled to the volatile memory subsystem, the non-volatile memory subsystem, the buffer memory, and the memory channel, wherein the module controller is configurable to:
receive a request from the memory controller to move one or more segments of data in a first Flash block in the main Flash to the DRAM; and
for each respective segment of data among the one or more segments of data:
determine a respective set of pages in the DRAM according to the request;
transfer respective data stored in the respective set of pages from the DRAM to the scratch Flash, the respective data occupying a corresponding segment in the scratch Flash; and
transfer the respective segment of data to the DRAM, the respective segment of data occupying the respective set of pages.

2. The memory module of claim 1 , wherein, to transfer the respective data stored in the respective set of pages from the DRAM to the scratch Flash, the module controller is further configurable to:
read the respective data from the DRAM;
write the respective data into the buffer memory;
read the respective data from the buffer memory; and
write the respective data into the scratch Flash.

3. The memory module of claim 2 , wherein, to transfer the respective segment of data to the DRAM, the module controller is further configurable to:
read the respective segment of data from the main Flash;
write the respective segment of data into the buffer memory;
read the respective segment of data from the buffer memory;
perform error correction on the respective segment of data to obtain respective error-corrected segment of data;
write the respective error-corrected segment of data into the buffer memory;
read the respective error-corrected segment of data from the buffer memory; and
write the respective error-corrected segment of data to the DRAM.

4. The memory module of claim 2 , wherein the scratch Flash includes a plurality of blocks including block j and block j+1, where j is a positive integer, and wherein a first subset of the set of pages are written into Block j in the scratch Flash, and a second subset of the set of pages is written into Block j+1 in the scratch Flash.

5. The memory module of claim 1 , wherein the respective data is transferred page by page from the DRAM to the scratch Flash.

6. The memory module of claim 1 , wherein the respective segment of data is transferred to the DRAM page by page.

7. The memory module of claim 1 , wherein the main Flash includes a plurality of blocks, and wherein the module controller is further configured to merge first data from a to-be-closed block in the DRAM with second data taken from the to-be-closed block in the DRAM and stored in the scratch Flash, so that the first data and the second data are stored in a same block in the main Flash.

8. A method, comprising:
at a memory module in a computer system, the computer system including a memory controller coupled to the memory module via a memory channel, the memory channel including a data bus and a control/address (C/A) bus, the memory module including a volatile memory subsystem coupled to the memory channel, a non-volatile memory subsystem, and buffer memory, the volatile memory subsystem including dynamic random access memory (DRAM), the non-volatile memory subsystem including Flash memory, the Flash memory including main Flash providing a main Flash memory space and scratch Flash providing a scratch Flash memory space,
receiving a request from the memory controller to move one or more segments of data in a first Flash block in the main Flash to the DRAM; and
for each respective segment of data among the one or more segments of data:
determining a respective set of pages in the DRAM according to the request;
transferring respective data stored in the respective set of pages from the DRAM to the scratch Flash, the respective data occupying a corresponding segment in the scratch Flash; and
transferring the respective segment of data to the DRAM, the respective segment of data occupying the respective set of pages.

9. The method of claim 8 , wherein transferring the respective data stored in the respective set of pages from the DRAM to the scratch Flash includes:
reading the respective data from the DRAM;
writing the respective data into the buffer memory;
reading the respective data from the buffer memory; and
writing the respective data into the scratch Flash.

10. The method of claim 9 , wherein the scratch Flash includes a plurality of blocks including block j and block j+1, where j is a positive integer, and wherein a first subset of the set of pages are written into Block j in the scratch Flash, and a second subset of the set of pages is written into Block j+1 in the scratch Flash.

11. The method of claim 8 , wherein transferring the respective segment of data to the DRAM includes:
reading the respective segment of data from the main Flash;
writing the respective segment of data into the buffer memory;
reading the respective segment of data from the buffer memory;
performing error correction on the respective segment of data to obtain respective error-corrected segment of data;
writing the respective error-corrected segment of data into the buffer memory;
reading the respective error-corrected segment of data from the buffer memory; and
writing the respective error-corrected segment of data to the DRAM.

12. The method of claim 8 , wherein the respective data is transferred page by page from the DRAM to the scratch Flash.

13. The method of claim 8 , wherein the respective segment of data is transferred to the DRAM page by page.

14. The method of claim 8 , wherein the main Flash includes a plurality of blocks, the method further comprising merging first data from a to-be-closed block in the DRAM with second data taken from the to-be-closed block in the DRAM and stored in the scratch Flash, whereby the first data and the second data are stored in a same block in the main Flash.

Assignees

• Netlist Inc

Inventors

• Lee Hyun
• Bhakta Jayesh R
• Chen Chi She
• Solomon Jeffery C
• Martinez Mario Jesus
• Le Hao
• Choi Soon J

Classifications

• G06F3/0688

  Non-volatile semiconductor memory arrays · CPC title

• G06F12/0871

  Allocation or management of cache space · CPC title

• G06F3/068

  Hybrid storage device · CPC title

• G06F2212/214

  Solid state disk · CPC title

• G06F3/0656

  Data buffering arrangements · CPC title