Vertically transitioning between substrate integrated waveguides (SIWs) within a multilayered printed circuit board (PCB)

US11658378B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11658378-B2
Application numberUS-201916600760-A
CountryUS
Kind codeB2
Filing dateOct 14, 2019
Priority dateOct 14, 2019
Publication dateMay 23, 2023
Grant dateMay 23, 2023

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  1. Title

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  2. Abstract

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  5. First independent claim

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  6. CPC / IPC classifications

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Abstract

Official abstract text for this publication.

Methods and apparatuses for vertically transitioning signals between substrate integrated waveguides within a multilayered printed circuit board (PCB) are disclosed. A first substrate integrated waveguide (SIW) is provided in a first layer of the PCB, the first SIW having a first terminal portion. A second SIW is provided in a second layer of the PCB, the second SIW having a second terminal portion that overlaps with the first terminal portion, wherein a first ground plane separates the first SIW and the second SIW. A vertical transition comprising an aperture in the first ground plane that is disposed in an area defined by the overlap of the first terminal portion and the second terminal portion, such that a signal propagated in the first SIW transitions to the second SIW in a different layer through the aperture.

First claim

Opening claim text (preview).

What is claimed is: 1. An apparatus configured for vertically transitioning signals between substrate integrated waveguides within a multilayered printed circuit board (PCB), comprising: a first substrate integrated waveguide (SIW) implemented in a first layer of the PCB, the first SIW having a first terminal portion; a second SIW implemented in a second layer of the PCB, the second SIW having a second terminal portion that overlaps with the first terminal portion; a first ground plane separating the first SIW and the second SIW; and a vertical transition comprising an aperture in the first ground plane that is disposed in an area defined by the overlap of the first terminal portion and the second terminal portion, wherein the first SIW includes a first set of ground vias crossing the first SIW adjacent to a first side of the aperture and the second SIW includes a second set of ground vias crossing the second SIW adjacent to a second side of the aperture, such that the first set of ground vias and the second set of ground vias guide a signal through the aperture from the first layer to the second layer, and wherein the first layer of the PCB and the second layer of the PCB are separated by one or more additional layers including a second ground plane having a second aperture corresponding to the aperture of the first ground plane, and wherein the first set of ground vias extends from a bottom of the first ground plane of the first SIW to the second ground plane, and wherein the second set of vias extend from the first ground plane to a top of the second ground plane of the second SIW. 2. The apparatus of claim 1 , wherein the first SIW comprises, disposed between the first ground plane and the second ground plane: a first dielectric layer, first side walls of periodic vias connecting the first ground plane and the second ground plane, and the first set of ground vias, connecting the first ground plane and the second ground plane, disposed perpendicular to and between the first side walls at the first terminal portion; and wherein the second SIW comprises, disposed between the first ground plane and a third ground plane: a second dielectric layer, second side walls of periodic vias connecting the first ground plane and the third ground plane, and the second set of ground vias, connecting the first ground plane and the third ground plane, disposed perpendicular to and between the second side walls at the second terminal portion. 3. The apparatus of claim 2 , wherein the first set of ground vias and the second set of ground vias at least partially define the overlap of the first terminal portion and the second terminal portion such that the aperture in the first ground plane is formed between connection points of the first set of ground vias and the second set of ground vias to the first ground plane. 4. The apparatus of claim 1 , wherein a width of the aperture is equal to a width of the waveguide of the first SIW and the second SIW, and wherein a length of the aperture is determined based on operational frequency, substrate material characteristics, and a thickness of the first ground plane, wherein the length of the aperture is oriented parallel to a direction of the overlap of the first terminal portion and the second terminal portion, and wherein the width of the aperture is oriented perpendicular to the direction of the overlap of the first terminal portion and the second terminal portion. 5. The apparatus of claim 1 , wherein the apparatus is a high-speed signaling bus channel. 6. A method of vertically transitioning a signal between a first substrate integrated waveguide (SIW) and a second SIW within a multilayered printed circuit board (PCB), comprising: providing the first SIW implemented in a first layer of the PCB, the first SIW having a first terminal portion, and providing the second SIW implemented in a second layer of the PCB, the second SIW having a second terminal portion that overlaps with the first terminal portion, wherein a first ground plane separates the first SIW and the second SIW; providing a vertical transition comprising an aperture in the first ground plane that is disposed in an area defined by the overlap of the first terminal portion and the second terminal portion, wherein the first SIW includes a first set of ground vias crossing the first SIW adjacent to a first side of the aperture and the second SIW includes a second set of ground vias crossing the second SIW adjacent to a second side of the aperture, such that the first set of ground vias and the second set of ground vias guide a signal through the aperture from the first layer to the second layer, and wherein the first layer of the PCB and the second layer of the PCB are separated by one or more additional layers including a second ground plane having a second aperture corresponding to the aperture of the first ground plane, and wherein the first set of ground vias extends from a bottom of the first ground plane of the first SIW to the second ground plane, and wherein the second set of vias extend from the first ground plane to a top of the second ground plane of the second SIW; propagating a signal in the first SIW; and receiving the signal in the second SIW through the apertures. 7. The method of claim 6 , wherein a width of the aperture is equal to a width of the waveguide of the first SIW and the second SIW, and wherein a length of the aperture is determined based on operational frequency, substrate material characteristics, and a thickness of the first ground plane, wherein the length of the aperture is oriented parallel to a direction of the overlap of the first terminal portion and the second terminal portion, and wherein the width of the aperture is oriented perpendicular to the direction of the overlap of the first terminal portion and the second terminal portion. 8. The method of claim 6 , wherein the first SIW and the second SIW serve as a high speed signaling bus channel within which a high speed signal propagates. 9. The method of claim 6 , wherein providing the first SIW in the first layer of the PCB includes placing between the first ground plane and the second ground plane: a first dielectric layer, first side walls of periodic vias connecting the first ground plane and the second ground plane, and the first set of ground vias, connecting the first ground plane and the second ground plane, disposed perpendicular to and between the first side walls at the first terminal portion; and wherein providing the second SIW in the second layer of the PCB includes placing between the first ground plane and a third ground plane: a second dielectric layer, second side walls of periodic vias connecting the first ground plane and the third ground plane, and the second set of ground vias, connecting the first ground plane and the third ground plane, disposed perpendicular to and between the second side walls at the second terminal portion. 10. The method of claim 9 , wherein the first set of ground vias and the second set of ground vias at least partially define the overlap of the first terminal portion and the second terminal portion such that the aperture in the first ground plane is formed between connection points of the first set of ground vias and the second set of ground vias to the first ground plane. 11. A multilayered printed circuit board (PCB) comprising: a first substrate integrated waveguide (SIW) implemented in a first layer of the PCB, the first SIW having a first terminal portion; a second SIW implemented in a second layer of the PCB, the second SIW having a second terminal portion that overlaps with the first terminal portion; a first ground plane separating the firs

Assignees

Inventors

Classifications

  • Lands, clearance holes or other lay-out details concerning the surrounding of a via · CPC title

  • H01P5/024Primary

    between hollow waveguides · CPC title

  • H01P5/02Primary

    with invariable factor of coupling (H01P5/12 takes precedence {choke joints H01P1/04, H01P1/06}) · CPC title

  • Grounding of printed circuits by connection to external grounding means · CPC title

  • Hollow waveguide joints · CPC title

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What does patent US11658378B2 cover?
Methods and apparatuses for vertically transitioning signals between substrate integrated waveguides within a multilayered printed circuit board (PCB) are disclosed. A first substrate integrated waveguide (SIW) is provided in a first layer of the PCB, the first SIW having a first terminal portion. A second SIW is provided in a second layer of the PCB, the second SIW having a second terminal por…
Who is the assignee on this patent?
IBM
What technology area does this patent fall under?
Primary CPC classification H01P5/024. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue May 23 2023 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).