Vertical trench gate MOSFET with integrated Schottky diode

Patent metadata

Field	Value
Publication number	US-11658241-B2
Application number	US-201816237210-A
Country	US
Kind code	B2
Filing date	Dec 31, 2018
Priority date	Dec 31, 2018
Publication date	May 23, 2023
Grant date	May 23, 2023

Abstract

An integrated circuit includes a trench gate MOSFET including MOSFET cells. Each MOSFET cell includes an active trench gate in an n-epitaxial layer oriented in a first direction with a polysilicon gate over a lower polysilicon portion. P-type body regions are between trench gates and are separated by an n-epitaxial region. N-type source regions are located over the p-type regions. A gate dielectric layer is between the polysilicon gates and the body regions. A metal-containing layer contacts the n-epitaxial region to provide an anode of an embedded Schottky diode. A dielectric layer over the n-epitaxial layer has metal contacts therethrough connecting to the n-type source regions, to the p-type body regions, and to the anode of the Schottky diode.

First claim

The invention claimed is:

1. A method of fabricating an integrated circuit, comprising;
forming a first vertical trench gate transistor within an n-type semiconductor substrate having a top surface, the first vertical trench gate transistor comprising:
a first n-type region located at the top surface and between a first trench gate and a metal contact; and
a first p-type region located between the first n-type region and the n-type semiconductor substrate;

forming a second vertical trench gate transistor within the n-type semiconductor substrate, the second vertical trench gate transistor comprising:
a second n-type region located at the top surface and between the first trench gate and the metal contact; and
a second p-type region located between the second n-type region and the n-type substrate, and

forming a Schottky contact to the n-type semiconductor substrate, thereby forming a Schottky diode between the first and second vertical trench gate transistors, the Schottky contact located above a bottom boundary between the p-type regions and the n-type semiconductor substrate and comprising a metal-containing layer located directly on the n-type semiconductor substrate, and
electrically connecting to the first vertical trench gate transistor to the second vertical trench gate transistor, and to the Schottky diode.

2. The method of claim 1 , wherein the metal-containing layer comprises TiN or TaN.

3. The method of claim 1 , wherein the first and second n-type regions are configured to operate as first and second source regions, respectively, of the first and second vertical trench gate transistors.

4. The method of claim 1 , wherein the first and second vertical trench gate transistors include respective first and second polysilicon gates, and further comprising forming a recess in each of the first and second polysilicon gates.

5. The method of claim 1 , wherein the metal-containing layer connects the first n-type region to the first p-type region, and connects the second n-type region to the second p-type region.

6. The method of claim 1 , wherein the forming the Schottky contact includes etching through the first and second n-type regions and into the first and second p-type regions.

7. The method of claim 1 , wherein a thickness of the metal-containing layer is within a range between about 10 nm and about 50 nm.

8. A method of fabricating an integrated circuit, comprising:
forming first and second trenches within a lightly doped n-type epitaxial layer over a semiconductor substrate;
forming first and second p-type body regions between the first and second trenches, and respective first and second n-type source regions over the first and second body regions, the first and second p-type body regions interfacing the n-type epitaxial layer at a first elevation above the substrate;
forming a metal or metallic compound layer that touches the first and second body regions and the first and second source regions, and touches the epitaxial layer at a second elevation above the substrate greater than the first elevation.

9. The method of claim 8 , wherein the metal or metallic compound layer comprises TiN or TaN.

10. The method of claim 8 , wherein the metal or metallic compound layer comprises a refractory metal.

11. The method of claim 8 , further comprising forming respective first and second polysilicon field plates within the first and second trenches, and forming respective first and second polysilicon gates over the first and second field plates.

12. The method of claim 8 , wherein the metal or metallic compound layer forms a Schottky contact with the lightly doped n-type epitaxial layer.

13. The method of claim 12 , wherein forming the Schottky contact includes etching through the first and second source regions and into the first and second body regions.

14. The method of claim 8 , wherein a thickness of the metal or metallic compound layer is within a range between about 10 nm and about 50 nm.

15. The method of claim 8 , wherein the first and second source regions are respective portions of first and second vertical trench gate MOSFETs, the first and second vertical trench gate MOSFETs being part of a two-dimensional array of vertical trench gate MOSFETs, each neighboring pair of vertical trench gate MOSFETs being separated by a corresponding Schottky contact for which the metal or metallic compound layer contacts the n-type epitaxial layer.

16. The method of claim 15 , wherein the semiconductor substrate is configured to operate as a drain region of the first and second vertical trench gate MOSFETs.

17. The method of claim 8 , wherein the metal or metallic compound layer connects the first n-type region to the first p-type region, and connects the second n-type region to the second p-type region.

18. The method of claim 8 , wherein the first and second body regions are contiguously connected at a third elevation between the first elevation and the second elevation.

19. A method of fabricating an integrated circuit, comprising:
forming first and second trenches within a lightly doped n-type epitaxial layer over a semiconductor substrate;
forming first and second p-type body regions between the first and second trenches, and respective first and second n+ source regions over the first and second body regions, the first and second p-type body regions extending from a first elevation above the substrate to a second elevation above the substrate;
forming a metal or metallic compound layer that touches the first and second body regions and the first and second source regions, and touches the epitaxial layer between the first and second body regions at a third elevation between the first and second elevations.

20. The method of claim 19 , wherein the metal or metallic compound layer forms a Schottky contact with the lightly doped n-type epitaxial layer.

Assignees

• Texas Instruments Inc

Inventors

• Kim Sunglyong
• Sridhar Seetharaman
• Yang Hong
• Chen Ya Ping
• Grebs Thomas Eugene

Classifications

• H10D84/0135

  Manufacturing their gate conductors · CPC title

• H10D84/83

  of only insulated-gate FETs [IGFET] · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D84/016

  the components including vertical IGFETs · CPC title

• H10D64/513

  within recesses in the substrate, e.g. trench gates, groove gates or buried gates · CPC title