Stacked dies and methods for forming bonded structures

US11658173B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11658173-B2
Application numberUS-202017131329-A
CountryUS
Kind codeB2
Filing dateDec 22, 2020
Priority dateMay 19, 2016
Publication dateMay 23, 2023
Grant dateMay 23, 2023

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  1. Title

    What the patent document calls the invention.

  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

In various embodiments, a method for forming a bonded structure is disclosed. The method can comprise mounting a first integrated device die to a carrier. After mounting, the first integrated device die can be thinned. The method can include providing a first layer on an exposed surface of the first integrated device die. At least a portion of the first layer can be removed. A second integrated device die can be directly bonded to the first integrated device die without an intervening adhesive.

First claim

Opening claim text (preview).

What is claimed is: 1. A method for forming a bonded structure, the method comprising: mounting a first side of a first singulated integrated device die to a carrier, the first singulated integrated device die comprising a conductive via extending at least partially through the first singulated integrated device die; after mounting, providing a protective material comprising a first layer on the first integrated device die; and after providing the protective material, thinning the first integrated device die from a second side opposite the first side to expose the conductive via. 2. The method of claim 1 , further comprising removing at least a portion of the first layer and exposing the conductive via. 3. The method of claim 1 , wherein the first side comprises a frontside of the first singulated integrated device die and wherein the second side comprises a backside of the first singulated integrated device die, the method comprising removing at least a portion of the backside of the first singulated integrated device die. 4. The method of claim 1 , wherein the providing the protective material comprises providing a second layer on the first layer and thinning the first integrated device die comprises removing at least a portion of the second layer. 5. The method of claim 1 , wherein the first layer comprises a silicon-based dielectric. 6. The method of claim 1 , wherein the first layer is harder than a bulk material of the first integrated device die. 7. The method of claim 1 , wherein the providing the protective material comprises depositing the protective material to a thickness no less than a thickness of the first integrated device die, the thickness of the first integrated device die defined between a back surface and a front surface of the first integrated device die after the thinning. 8. The method of claim 7 , wherein the thickness of the first integrated device die is less than 20 microns after the thinning. 9. The method of claim 1 , further comprising directly hybrid bonding a second integrated device die to the first integrated device die without an intervening adhesive. 10. The method of claim 1 , wherein the providing the protective material comprises providing the first layer along at least a side surface of the first singulated integrated device die. 11. The method of claim 10 , wherein the providing the protective material comprises providing the first layer along a back surface of the first singulated integrated device die. 12. The method of claim 1 , wherein the thinning the first integrated device die from the second side opposite the first side to expose the conductive via comprises removing a portion of a liner from the conductive via. 13. The method of claim 1 , further comprising providing a redistribution layer (RDL) over at least a portion of the protective material. 14. The method of claim 13 , further comprising mounting a second integrated device die on the RDL. 15. The method of claim 1 , further comprising singulating the carrier into a plurality of singulated structures. 16. The method of claim 1 , wherein mounting the first singulated integrated device die to the carrier comprises directly bonding the first singulated integrated device die to the carrier without an adhesive. 17. The method of claim 4 , wherein the first layer and the second layer comprise a silicon-based dielectric. 18. A method for forming a bonded structure, the method comprising: directly bonding a nonconductive region of a first singulated integrated device die to a corresponding nonconductive region of a redistribution layer (RDL) of a carrier without an intervening adhesive; directly bonding a conductive contact of the first singulated integrated device die to a corresponding conductive contact of the RDL without an intervening adhesive; directly bonding a second singulated integrated device to the RDL, the second singulated integrated device die laterally spaced apart from the first singulated integrated device die; providing a protective material on the first integrated device die and the second integrated device die; and after providing the protective material, thinning the first and second integrated device dies. 19. The method of claim 18 , wherein the first singulated integrated device die comprises a conductive via, the method further comprising removing a portion of the protective material and exposing the conductive via. 20. The method of claim 18 , further comprising directly bonding a third singulated integrated device die to the first singulated integrated device die without an adhesive. 21. A method comprising: mounting a first integrated device die to a carrier, the first integrated device die having a first thickness; mounting a second integrated device die to the carrier, the second integrated device die having a second thickness different from the first thickness; providing a protective material over the first and second integrated device dies, the protective material comprising an inorganic dielectric material; and after providing the protective material, thinning the first and second integrated device dies. 22. The method of claim 21 , wherein the mounting the first integrated device die comprises directly bonding the first integrated device die to the carrier without an intervening adhesive. 23. The method of claim 21 , wherein the providing the protective material comprises providing a plurality of protective layers over the first and second integrated device dies. 24. The method of claim 21 , wherein thinning the first and second integrated device dies comprises removing at least a portion of the protective material. 25. The method of claim 21 , wherein at least one of the first and second thicknesses is in a range of 200 microns to 1000 microns before the thinning. 26. The method of claim 21 , wherein, after the thinning, the first and second integrated device dies have the same thickness. 27. The method of claim 21 , wherein mounting the first integrated device die to the carrier comprises directly hybrid bonding the first integrated device die to the carrier without an adhesive.

Assignees

Inventors

Classifications

  • for supporting or gripping · CPC title

  • Grinding, lapping or polishing of wafers, substrates or parts of devices · CPC title

  • characterised by their composition, e.g. multilayer masks or materials · CPC title

  • Etching of wafers, substrates or parts of devices · CPC title

  • between stacked chips · CPC title

Patent family

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Frequently asked questions

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What does patent US11658173B2 cover?
In various embodiments, a method for forming a bonded structure is disclosed. The method can comprise mounting a first integrated device die to a carrier. After mounting, the first integrated device die can be thinned. The method can include providing a first layer on an exposed surface of the first integrated device die. At least a portion of the first layer can be removed. A second integrated…
Who is the assignee on this patent?
Adeia Semiconductor Bonding Technologies Inc
What technology area does this patent fall under?
Primary CPC classification H10W74/014. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue May 23 2023 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).