Pixel circuit and method of driving the same, display panel

US11657759B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11657759-B2
Application numberUS-202217859159-A
CountryUS
Kind codeB2
Filing dateJul 7, 2022
Priority dateJan 10, 2018
Publication dateMay 23, 2023
Grant dateMay 23, 2023

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A pixel circuit and a method of driving the same, and a display panel. The pixel circuit includes a drive circuit, a data writing circuit, a compensating circuit, a reset circuit and a first light emitting control circuit. The drive circuit is configured to control a drive current for driving a light emitting element to emit light; the data writing circuit is configured to write a data signal to the first terminal of the drive circuit; the compensating circuit is configured to compensate the drive circuit; the reset circuit is configured to apply a reset voltage to the control terminal of the drive circuit and the first terminal of the light emitting element; the first light emitting control circuit is configured to apply a first voltage of the first voltage terminal to the first terminal of the drive circuit.

First claim

Opening claim text (preview).

What is claimed is: 1. A pixel circuit, comprising a drive circuit, a data writing circuit, a compensating circuit, a reset circuit, a first light emitting control circuit, and a second light emitting control circuit, wherein the drive circuit comprises a control terminal, a first terminal and a second terminal, and the drive circuit is configured to control a drive current for driving a light emitting element to emit light; the data writing circuit is coupled to the first terminal of the drive circuit, and the data writing circuit is configured to write a data signal to the first terminal of the drive circuit in response to a scan signal; the compensating circuit is coupled to the control terminal and the second terminal of the drive circuit and a first voltage terminal, and the compensating circuit is configured to compensate the drive circuit in response to the scan signal and the written data signal; the reset circuit is coupled to the control terminal of the drive circuit and the light emitting element, and the reset circuit is configured to apply a reset voltage to the control terminal of the drive circuit and the first terminal of the light emitting element in response to a reset signal; and the first light emitting control circuit is coupled to the first terminal of the drive circuit, and the first light emitting control circuit is configured to apply a first voltage of the first voltage terminal to the first terminal of the drive circuit in response to a first light emitting control signal, wherein at an initialization stage, the reset circuit is configured to receive the reset signal to apply the reset voltage to the first node and the fourth node, the second light emitting control circuit is configured to be turned on to receive the second light emitting control signal to apply the reset voltage to the third node, and the first light emitting control circuit is configured to be turned off; at a data writing and compensating stage, the data writing circuit is configured to receive the scan signal to apply the data signal to the second node, and the compensating circuit is configured to receive the scan signal to compensate the drive circuit; at a pre-light emitting stage, the first light emitting control circuit is configured to be turned on to receive the first light emitting control signal to apply the first voltage to the second node, and the second light emitting control circuit is configured to be turned off; and at a light emitting stage, the first light emitting control circuit is configured to receive the first light emitting control signal and the second light emitting control circuit is configured to receive the second light emitting control signal, such that the second light emitting control circuit applies the drive current to the light emitting element to emit light. 2. The pixel circuit according to claim 1 , wherein a first terminal and a second terminal of the second light emitting control circuit are coupled to a first terminal of the light emitting element and the second terminal of the drive circuit respectively, and the first terminal and the second terminal of the second light emitting control circuit are configured to apply the drive current to the light emitting element in response to the second light emitting control signal. 3. The pixel circuit according to claim 1 , wherein the drive circuit comprises a first transistor; a gate of the first transistor is used as the control terminal of the drive circuit, a first electrode of the first transistor is used as the first terminal of the drive circuit, and a second electrode of the first transistor is used as the second terminal of the drive circuit. 4. The pixel circuit according to claim 1 , wherein the data writing circuit comprises a second transistor; a gate of the second transistor is used as a control terminal of the data writing circuit and is configured to be coupled to a scan line to receive the scan signal, a first electrode of the second transistor is used as a first terminal of the data writing circuit and is configured to be coupled to a data line to receive the data signal, and a second electrode of the second transistor is used as a second terminal of the data writing circuit and is coupled to the first terminal of the drive circuit. 5. The pixel circuit according to claim 1 , wherein the compensating circuit comprises a third transistor and a capacitor; a gate of the third transistor is coupled to a scan line to receive the scan signal, a first electrode of the third transistor is coupled to the control terminal of the drive circuit, a second electrode of the third transistor is coupled to the second terminal of the drive circuit; and a first electrode of the capacitor is coupled to the control terminal of the drive circuit, a second electrode of the capacitor is coupled to the first voltage terminal to receive a first voltage. 6. The pixel circuit according to claim 1 , wherein the reset circuit comprises a fourth transistor and a fifth transistor; a gate of the fourth transistor is coupled to a reset control line to receive the reset signal, a first electrode of the fourth transistor is coupled to the control terminal of the drive circuit, and a second electrode of the fourth transistor is coupled to a reset voltage terminal to receive the reset voltage; and a gate of the fifth transistor is coupled to the reset control line to receive the reset signal, a first electrode of the fifth transistor is coupled to the first terminal of the light emitting element, and a second electrode of the fifth transistor is coupled to the reset voltage terminal to receive the reset voltage. 7. The pixel circuit according to claim 1 , wherein the first light emitting control circuit comprises a sixth transistor; a gate of the sixth transistor is used as a control terminal of the first light emitting control circuit and is configured to be coupled to a first light emitting control line to receive the first light emitting control signal, a first electrode of the sixth transistor is used as a first terminal of the first light emitting control circuit, and is configured to be coupled to the first voltage terminal to receive the first voltage, and a second electrode of the sixth transistor is used as a second terminal of the first light emitting control circuit and is coupled to the first terminal of the drive circuit. 8. The pixel circuit according to claim 2 , wherein the second light emitting control circuit comprises a seventh transistor; a gate of the seventh transistor is used as a control terminal of the second light emitting control circuit, and is coupled to a second light emitting control line to receive the second light emitting control signal, a first electrode of the seventh transistor is used as the second terminal of the second light emitting control circuit and is coupled to the second terminal of the drive circuit, and a second electrode of the seventh transistor is used as the first terminal of the second light emitting control circuit and is coupled to the first terminal of the light emitting element. 9. The pixel circuit according to claim 2 , wherein the first light emitting control signal and the second light emitting control signal are both turn-on signals in part of a period. 10. The pixel circuit according to claim 1 , wherein the drive circuit is configured to be turned on at the pre-light emitting stage, and wherein a voltage of the second terminal of the drive circuit is relate to the first voltage of the first voltage terminal. 11. The pixel circuit according to claim 1 , wherein a potential of the first voltage of the first voltage terminal is higher than a potentia

Assignees

Inventors

Classifications

  • Details of timing specific for flat panels, other than clock recovery · CPC title

  • with pixel circuitry controlling the voltage across the light-emitting element · CPC title

  • used for counteracting undesired variations, e.g. feedback or autozeroing · CPC title

  • by means of changes in the pixel supply voltage · CPC title

  • Compensation of drifts in the characteristics of light emitting or modulating elements · CPC title

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What does patent US11657759B2 cover?
A pixel circuit and a method of driving the same, and a display panel. The pixel circuit includes a drive circuit, a data writing circuit, a compensating circuit, a reset circuit and a first light emitting control circuit. The drive circuit is configured to control a drive current for driving a light emitting element to emit light; the data writing circuit is configured to write a data signal t…
Who is the assignee on this patent?
Boe Technology Group Co Ltd
What technology area does this patent fall under?
Primary CPC classification G09G3/3233. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue May 23 2023 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 4 related publications on this page (citations in our corpus or others sharing the same primary CPC).