Display apparatus and method of driving the same

US2016133191A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2016133191-A1
Application numberUS-201514735484-A
CountryUS
Kind codeA1
Filing dateJun 10, 2015
Priority dateNov 12, 2014
Publication dateMay 12, 2016
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A display apparatus includes pixels connected to scan lines, data lines, and emission control lines. Each include includes an organic light-emitting diode (OLED), a first transistor to transfer driving current to the OLED based on a data signal, a second transistor to transfer the data signal to the first transistor based on a first scan signal having a gate-on voltage level during a data writing period, a first capacitor connected between a gate electrode of the first transistor and a first power source, and a second capacitor connected between a drain electrode of the first transistor and the first power source.

First claim

Opening claim text (preview).

What is claimed is: 1 . A display apparatus, comprising: a display unit including a plurality of pixels connected to a plurality of scan lines, a plurality of data lines, and a plurality of emission control lines, wherein each of the pixels includes: an organic light-emitting diode (OLED); a first transistor to transfer driving current, based on a data signal, to the OLED; a second transistor to transfer the data signal to the first transistor based on a first scan signal having a gate-on voltage level during a data writing period; a first capacitor connected between a gate electrode of the first transistor and a first power source; and a second capacitor connected between a drain electrode of the first transistor and the first power source. 2 . The display apparatus as claimed in claim 1 , wherein: the gate electrode of the first transistor is connected to a first node, and the first node connects the first transistor to the second transistor. 3 . The display apparatus as claimed in claim 1 , wherein each of the pixels includes a third transistor to supply an initialization voltage to the gate electrode of the first transistor, in order to initialize a characteristic of the first transistor based on a second scan signal having the gate-on voltage level during an initialization period. 4 . The display apparatus as claimed in claim 3 , wherein the second scan signal has the gate-on voltage level during a unit scan period immediately before the data writing period. 5 . The display apparatus as claimed in claim 3 , wherein the second scan signal has the gate-on voltage level during one or more unit scan periods before the data writing period. 6 . The display apparatus as claimed in claim 5 , wherein the first scan signal has the gate-on voltage level during a unit scan period before a unit scan period in which the second scan signal has the gate-on voltage level. 7 . The display apparatus as claimed in claim 3 , wherein: the second scan signal has the gate-on voltage level during two or more unit scan periods before the data writing period, and the first scan signal has the gate-on voltage level during a unit scan period between two or more unit scan periods in which the second scan signal has the gate-on voltage level. 8 . The display apparatus as claimed in claim 3 , wherein: the second scan signal has the gate-on voltage level during two or more unit scan periods before the data writing period, and a period between two or more unit scan periods in which the second scan signal has the gate-on voltage level is multiples of a unit scan period. 9 . The display apparatus as claimed in claim 3 , wherein: the first scan signal has the gate-on voltage level during one or more unit scan periods before the data writing period, and the second scan signal has the gate-on voltage level during a unit scan period immediately before a unit scan period in which the first scan signal has the gate-on voltage level before the data writing period and/or a unit scan period immediately after a unit scan period in which the first scan signal has the gate-on voltage level. 10 . The display apparatus as claimed in claim 3 , wherein the initialization period is prior to the data writing period. 11 . The display apparatus as claimed in claim 1 , wherein each of the pixels includes a fourth transistor that diode-connects the first transistor based on the first scan signal having the gate-on voltage level during the data writing period. 12 . The display apparatus as claimed in claim 1 , wherein each of the pixels includes a fifth transistor to supply the initialization voltage to an anode electrode of the OLED based on a third scan signal. 13 . The display apparatus as claimed in claim 12 , wherein the third scan signal is equal to the first scan signal. 14 . The display apparatus as claimed in claim 1 , wherein each of the pixels includes sixth transistor to turn on based on a emission control signal, the sixth transistor connected to the second capacitor in parallel. 15 . The display apparatus as claimed in claim 1 , wherein each of the pixels includes a seventh transistor to connect the first transistor to the OLED based on an emission control signal. 16 . The display apparatus as claimed in claim 1 , further comprising: a scan driver to transfer scan signals through the scan lines; a data driver to transfer data signals through the data lines; and an emission driver to transfer emission control signals through the emission control lines. 17 . A method for driving a display apparatus, the method comprising: initializing a characteristic of the driving transistor; compensating for a threshold voltage of the driving transistor and transferring a data signal to the driving transistor; and emitting light from the OLED based on driving current corresponding to the data signal, wherein initializing the characteristic includes: transferring a first scan signal having a gate-on voltage level at least one time; and transferring a second scan signal having the gate-on voltage level at least one time. 18 . The method as claimed in claim 17 , wherein the first scan signal has the gate-on voltage level during a unit scan period before a unit scan period in which the second scan signal has the gate-on voltage level. 19 . The method as claimed in claim 17 , wherein the first scan signal has the gate-on voltage level during a unit scan period between two or more unit scan periods in which the second scan signal has the gate-on voltage level. 20 . The method as claimed in claim 17 , wherein: the second scan signal has the gate-on voltage level during two or more unit scan periods, and a period between two or more unit scan periods in which the second scan signal has the gate-on voltage level is multiples of a unit scan period.

Assignees

Inventors

Classifications

  • Compensation of drifts in the characteristics of light emitting or modulating elements · CPC title

  • Interleaved control phases for different scan lines in the same sub-field, e.g. initialization, addressing and sustaining in plasma displays that are not simultaneous for all scan lines · CPC title

  • Supplementary capacities in pixels having special driving circuits and electrodes instead of being connected to common electrode or ground; Use of additional capacitively coupled compensation electrodes · CPC title

  • with level shifting · CPC title

  • Compensation electrodes or other additional electrodes in matrix displays related to distortions or compensation signals, e.g. for modifying TFT threshold voltage in column driver · CPC title

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What does patent US2016133191A1 cover?
A display apparatus includes pixels connected to scan lines, data lines, and emission control lines. Each include includes an organic light-emitting diode (OLED), a first transistor to transfer driving current to the OLED based on a data signal, a second transistor to transfer the data signal to the first transistor based on a first scan signal having a gate-on voltage level during a data writi…
Who is the assignee on this patent?
Samsung Display Co Ltd
What technology area does this patent fall under?
Primary CPC classification G09G3/3258. Mapped technology areas include Physics.
When was this patent published?
Publication date Thu May 12 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).