Low-power compute-in-memory bitcell

Patent metadata

Field	Value
Publication number	US-11657238-B2
Application number	US-202016779491-A
Country	US
Kind code	B2
Filing date	Jan 31, 2020
Priority date	Jan 31, 2020
Publication date	May 23, 2023
Grant date	May 23, 2023

Abstract

A compute-in-memory bitcell is provided that includes a pair of cross-coupled inverter for storing a stored bit. The compute-in-memory bitcell includes a logic gate for multiplying the stored bit with an input vector bit. An output node for the logic gate connects to a second plate of a capacitor. A first plate of the capacitor connects to a read bit line.

First claim

We claim:

1. A compute-in-memory storage cell, comprising:
a pair of cross-coupled inverters having a first output node for a stored bit;
a read bit line;
a word line having a voltage responsive to an input bit;
a capacitor having a first plate connected to the read bit line; and
a first pass transistor connected between the first output node and a second plate of the capacitor and having a gate connected to the word line,
wherein the pair of cross-coupled inverters include a second output node for a complement of the stored bit the compute-in-memory storage cell further comprising:
a complement word line having a voltage responsive to a complement of the input bit;
a second pass transistor connected between the second output node and the second plate of the capacitor and having a gate connected to the complement word line.

2. The compute-in-memory storage cell of claim 1 , wherein the first pass transistor and the second pass transistor are both p-type metal-oxide semiconductor (PMOS) transistors.

3. The compute-in-memory storage cell of claim 1 , further comprising:
a read word line; and
a third transistor connected between the second plate of the capacitor and ground and having a gate connected to the read word line.

4. The compute-in-memory storage cell of claim 3 , wherein the third transistor is an n-type metal-oxide semiconductor (NMOS) transistor having a source connected to ground and a drain connected to the second plate of the capacitor.

5. The compute-in-memory storage cell of claim 3 , further comprising:
a fourth transistor connected between a power supply node for a power supply voltage and the read bit line.

6. The compute-in-memory storage cell of claim 5 , wherein the fourth transistor is a PMOS transistor having a source connected to the power supply node and a drain connected to the read bit line.

7. The compute-in-memory storage cell of claim 6 , further comprising:
a reset line for a reset signal, wherein a gate for the fourth transistor is connected to the reset line.

8. The compute-in-memory storage cell of claim 1 , further comprising:
a write bit line;
a complement write bit line:
a first access transistor connected between the write bit line and the first output node; and
a second access transistor connected between the complement write bit line and the second output node.

9. The compute-in-memory storage cell of claim 8 , further comprising:
a write word line, wherein the write word line is connected to a gate of the first access transistor and is connected to a gate of the second access transistor.

10. The compute-in-memory storage cell of claim 5 , further comprising a fifth transistor connected between the second plate of the capacitor and the power supply node.

11. The compute-in-memory storage cell of claim 1 , wherein the compute-in-memory storage cell is included within a column in an array of compute-in-memory storage cells.

12. The compute-in-memory storage cell of claim 1 , wherein the capacitor is selected from the group consisting of a metal-layer capacitor, a varactor, and a metal-insulator-metal capacitor.

13. The compute-in-memory storage cell of claim 4 , wherein the third transistor is a thick-oxide transistor.

14. A compute-in-memory storage cell, comprising:
a pair of cross-coupled inverters having a first output node for a stored bit;
a read bit line;
a capacitor having a first plate connected to the read bit line;
a first transmission gate connected between the first output node and a second plate of the capacitor, wherein the first transmission gate is configured to close in response to an input bit being true and is configured to open in response to the input bit being false;
a read word line; and
a first transistor connected between the second plate of the capacitor and ground and having a gate connected to the read word line.

15. The compute-in-memory storage cell of claim 14 , wherein the pair of cross-coupled inverters include a second output node for a complement of the stored bit; the compute-in-memory storage cell further comprising:
a second transmission gate connected between the second output node and the second plate of the capacitor, wherein the second transmission gate is configured to open in response to the input bit being true and is configured to close in response to the input bit being false.

16. The compute-in-memory storage cell of claim 14 , wherein the input bit is an active-low signal.

17. The compute-in-memory storage cell of claim 14 , wherein the first transistor is a n-type metal-oxide semiconductor (NMOS) transistor having a source connected to ground and a drain connected to the second plate of the capacitor.

18. The compute-in-memory storage cell of claim 14 , further comprising:
a second transistor connected between a power supply node for a power supply voltage and the read bit line.

19. The compute-in-memory storage cell of claim 18 , wherein the second transistor is a PMOS transistor having a source connected to the power supply node and a drain connected to the read bit line.

20. The compute-in-memory storage cell of claim 19 , further comprising:
a reset line for a reset signal, wherein a gate for the second transistor is connected to the reset line.

Assignees

• Qualcomm Inc

Inventors

• Srivastava Ankit
• Mirhaj Seyed Arash
• Miao Guoqing
• Bazarjani Seyfi

Classifications

• G06G7/12 Primary

  Arrangements for performing computing operations, e.g. {operational} amplifiers specially adapted therefor · CPC title

• G06G7/16

  for multiplication or division {(G06G7/19 and G06G7/24 take precedence; measuring electric power G01R21/00)} · CPC title

• G11C11/54

  using elements simulating biological cells, e.g. neuron · CPC title

• G11C7/1006

  Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor · CPC title

• G11C11/412

  using field-effect transistors only · CPC title