Wafer sensitivity determination and communication

Patent metadata

Field	Value
Publication number	US-11657207-B2
Application number	US-202117378423-A
Country	US
Kind code	B2
Filing date	Jul 16, 2021
Priority date	Jul 28, 2020
Publication date	May 23, 2023
Grant date	May 23, 2023

Abstract

A method comprises receiving an integrated circuit (IC) chip design, and generating, by one or more processors, a wafer image and a wafer target from the IC chip design. The method further comprises generating, by the one or more processors, sensitivity information based on a determination that the wafer image and the wafer target converge, and outputting the sensitivity information. The sensitivity information is associated with writing a mask written for the IC chip design.

First claim

What is claimed is:

1. A method comprising:
receiving an integrated circuit (IC) chip design;
generating, by one or more processors, a wafer image and a wafer target from the IC chip design;
determining that the wafer image and the wafer target converge based on a difference between the wafer image and the wafer target being less than a threshold;
generating, by the one or more processors, sensitivity information based on the determination that the wafer image and the wafer target converge; and
outputting the sensitivity information, wherein the sensitivity information is associated with writing a mask written for the IC chip design.

2. The method of claim 1 further comprising:
determining a mask design file from the IC chip design; and
outputting the mask design file from a mask synthesis engine to a mask writing device, wherein the sensitivity information indicates a sensitivity of one or more polygons of the IC chip design to mask writing errors.

3. The method of claim 1 further comprising:
generating a mask representation from the IC chip design; and
simulating the mask representation to generate the wafer image.

4. The method of claim 3 further comprising modifying the mask representation based on a determination that the wafer image and the wafer target do not converge.

5. The method of claim 1 , wherein generating the sensitivity information comprises:
determining a sensitivity value at one or more points along a polygon within the IC chip design by perturbing one or more edges within a mask representation corresponding to the wafer image.

6. The method of claim 5 , wherein generating the sensitivity information further comprises altering a size of the polygon based on the sensitivity value.

7. The method of claim 1 , wherein generating the sensitivity information comprises determining one of sensitivity bands of a polygon within the IC chip design, variation amounts of the polygon, and gradation levels for the polygon.

8. A non-transitory computer readable medium comprising stored instructions, which when executed by a processor, cause the processor to:
receive an integrated circuit (IC) chip design;
generate a wafer image and a wafer target from the IC chip design;
determine that the wafer image and the wafer target converge based on a difference between the wafer image and the wafer target being less than a threshold;
generate sensitivity information based on the determination that the wafer image and the wafer target converge; and
output the sensitivity information to a mask writing device.

9. The non-transitory computer readable medium of claim 8 , wherein the processor is further caused to:
determine a mask design file from the IC chip design; and
output the mask design file to the mask design file from a mask synthesis engine to the mask writing device.

10. The non-transitory computer readable medium of claim 8 , wherein the processor is further caused to:
generate a mask representation from the IC chip design; and
simulate the mask representation to generate the wafer image.

11. The non-transitory computer readable medium of claim 10 , wherein the processor is further caused to modify the mask representation based on a determination that the wafer image and the wafer target do not converge.

12. The non-transitory computer readable medium of claim 8 , wherein generating the sensitivity information comprises:
determining a sensitivity value at one or more points along a polygon within the IC chip design by perturbing one or more edges within a mask representation corresponding to the wafer image.

13. The non-transitory computer readable medium of claim 12 , wherein generating the sensitivity information further comprises altering a size of the polygon based on the sensitivity value.

14. The non-transitory computer readable medium of claim 8 , wherein generating the sensitivity information comprises determining one of sensitivity bands of a polygon within the IC chip design, variation amounts of the polygon, and gradation levels for the polygon.

15. A lithography system comprising:
a memory; and
a processor coupled with the memory, the processor configured to:
receive an integrated circuit (IC) chip design;
generate a wafer image and a wafer target from the IC chip design;
determine that the wafer image and the wafer target converge based on a difference between the wafer image and the wafer target being less than a threshold;
generate sensitivity information based on the determination that the wafer image and the wafer target converge; and
output the sensitivity information to a mask writing device.

16. The lithography system of claim 15 , wherein the processor is further configured to:
determine a mask design file from the IC chip design; and
output the mask design file to the mask writing device.

17. The lithography system of claim 15 , wherein the processor is further configured to:
generate a mask representation from the IC chip design; and
simulate the mask representation to generate the wafer image.

18. The lithography system of claim 17 , wherein the processor is further configured to modify the mask representation based on a determination that the wafer image and the wafer target do not converge.

19. The lithography system of claim 15 , wherein generating the sensitivity information comprises:
determining a sensitivity value at one or more points along a polygon within the IC chip design by perturbing one or more edges within a mask representation corresponding to the wafer image.

20. The lithography system of claim 15 , wherein generating the sensitivity information comprises determining one of sensitivity bands of a polygon within the IC chip design, variation amounts of the polygon, and gradation levels for the polygon.

Assignees

• Synopsys Inc

Inventors

• Cecil Thomas

Classifications

• G06F30/392

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G03F1/00

  Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof · CPC title

• G06F2119/18

  Manufacturability analysis or optimisation for manufacturability · CPC title

• G03F1/76

  Patterning of masks by imaging · CPC title

• G06F30/39 Primary

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title