Integrated circuit layout design methodology with process variation bands

Patent metadata

Field	Value
Publication number	US-9977856-B2
Application number	US-201615174914-A
Country	US
Kind code	B2
Filing date	Jun 6, 2016
Priority date	May 7, 2004
Publication date	May 22, 2018
Grant date	May 22, 2018

Abstract

A system for analyzing IC layouts and designs by calculating variations of a number of objects to be created on a semiconductor wafer as a result of different process conditions. The variations are analyzed to determine individual feature failures or to rank layout designs by their susceptibility to process variations. In one embodiment, the variations are represented by PV-bands having an inner edge that defines the smallest area in which an object will always print and an outer edge that defines the largest area in which an object will print under some process conditions.

First claim

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. A method, comprising:
verifying an integrated circuit layout by:
generating representations of a plurality of variations in edge placement that are likely to occur in a particular circuit layer during manufacturing under respective, process conditions;
extracting electrical properties that will be associated with a circuit manufactured with these variations; and
evaluating electrical timing parameters of the circuit manufactured with these variations; and

following successful verification of the integrated circuit layout, forwarding the integrated circuit layout to a mask writing tool for production of one or more masks or reticles.

2. The method of claim 1 , wherein the evaluating electrical timing parameters comprises correlating the electrical timing parameters with a manufacturability index for a region of the integrated circuit layout.

3. The method of claim 1 , wherein the generating the representations is performed for only polysilicon layers.

4. The method of claim 1 , wherein the evaluating electrical timing parameters comprises comparing generated timing results for each of the process conditions.

5. The method of claim 1 , wherein the evaluating electrical timing parameters comprises using a transistor model to incorporate processing effects, including lithography, from statistical analysis of the process conditions.

6. The method of claim 1 , wherein the generated representations comprise a PV-hand including (1) an inner edge that defines an expected minimum area that a corresponding object in the integrated circuit layout will occupy on a wafer when printed under the process conditions and (2) an outer edge that defines a zone where edges of the corresponding object may be printed under the process conditions.

7. The method of claim 1 , wherein the generated representations comprise a PV-band including an outer edge that defines a zone where edges of a corresponding object in the integrated circuit layout may be printed under the process conditions.

8. One or more computer-readable storage devices storing instructions that when executed by a processor cause the processor to perform a method for verifying an integrated circuit layout, the method comprising:
generating representations of a plurality of variations in layout feature edges that are likely to occur in a particular circuit during manufacturing under respective photolithographic process conditions;
extracting electrical properties that will be associated with a circuit manufactured according to these variations; and
evaluating electrical timing parameters of the circuit when manufactured with these variations.

9. The computer-readable storage devices of claim 8 , wherein the evaluating electrical timing parameters comprises correlating the electrical timing parameters with a manufacturability index for a region of the integrated circuit layout.

10. The computer-readable storage devices of claim 8 , wherein the generating the representations is performed for only polysilicon layers.

11. The computer-readable storage devices of claim 8 , wherein the evaluating electrical timing parameters comprises comparing generated timing results for each of the process conditions.

12. The computer-readable storage devices of claim 8 , wherein the evaluating electrical timing parameters comprises using a transistor model to incorporate processing effects, including lithography, from statistical analysis of the process conditions.

13. The computer-readable storage devices of claim 8 , wherein the generated representations comprise a PV-band including (1) an inner edge that defines an expected minimum area that a corresponding object in the integrated circuit layout will occupy on a wafer when printed under the process conditions and (2) an outer edge that defines a zone where edges of the corresponding object may be printed under the process conditions.

14. The computer-readable storage devices of claim 8 , wherein the generated representations comprise a PV-band including an outer edge that defines a zone where edges of a corresponding object in the integrated circuit layout may be printed under the process conditions.

15. A system comprising:
one or more processors;
one or more computer-readable storage devices storing instructions that when executed by the processors cause the processors to perform a method for verifying an integrated circuit layout, the method comprising:
generating representations of a plurality of variations in layout feature edges that are likely to occur in a particular circuit during manufacturing under respective photolithographic process conditions;
extracting electrical properties that will be associated with a circuit manufactured according to these variations; and
evaluating electrical timing parameters of the circuit when manufactured with these variations.

16. The system of claim 15 , wherein the evaluating electrical timing parameters comprises correlating the electrical timing parameters with a manufacturability index for a region of the integrated circuit layout.

17. The system of claim 15 , wherein the generating the representations is performed for only polysilicon layers.

18. The system of claim 15 , wherein the evaluating electrical timing parameters comprises comparing generated timing results for each of the process conditions.

19. The system of claim 15 , wherein the evaluating electrical timing parameters comprises using a transistor model to incorporate processing effects, including lithography, from statistical analysis of the process conditions.

20. The system of claim 15 , wherein the generated representations comprise a PV-band including (1) an inner edge that defines an expected minimum area that a corresponding object in the integrated circuit layout will occupy on a wafer when printed under the process conditions and (2) an outer edge that defines a zone where edges of the corresponding object may be printed under the process conditions.

21. The system of claim 15 , wherein the generated representations comprise a PV-band including an outer edge that defines a zone where edges of a corresponding object in the integrated circuit layout may be printed under the process conditions.

Assignees

• Mentor Graphics Corp

Inventors

• Robles Juan Andres Torres

Classifications

• G06F30/33

  Design verification, e.g. functional simulation or model checking · CPC title

• G06F2119/18

  Manufacturability analysis or optimisation for manufacturability · CPC title

• G06F2119/12

  Timing analysis or timing optimisation · CPC title

• G06F2111/08

  Probabilistic or stochastic CAD · CPC title

• Y02T10/82

  Elements for improving aerodynamics · CPC title