Electroplating edge connector pins of printed circuit boards without using tie bars

US11653455B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11653455-B2
Application numberUS-202117186868-A
CountryUS
Kind codeB2
Filing dateFeb 26, 2021
Priority dateFeb 26, 2021
Publication dateMay 16, 2023
Grant dateMay 16, 2023

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  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

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  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method for forming a printed circuit board includes: forming on a substrate a first conductive layer for a first edge connector pin and a first conductive layer for a second edge connector pin, wherein the first conductive layer for the first edge connector pin and the first conductive layer for the second edge connector pin are electrically coupled to one another via a first conductive layer for an electrical bridging element; electroplating a second conductive layer onto both the first conductive layer for the first edge connector pin and the first conductive layer for the second edge connector pin via a plating current conductor; and removing at least a portion of the electrical bridging element to electrically separate the first edge connector pin from the second edge connector pin.

First claim

Opening claim text (preview).

What is claimed is: 1. A method for forming a printed circuit board, the method comprising: forming on a substrate a first conductive layer for a first edge connector pin and a first conductive layer for a second edge connector pin, wherein the first conductive layer for the first edge connector pin and the first conductive layer for the second edge connector pin are electrically coupled to one another via a first conductive layer for an electrical bridging element; electroplating a second conductive layer onto both the first conductive layer for the first edge connector pin and the first conductive layer for the second edge connector pin via a plating current conductor; and removing at least a portion of the electrical bridging element to electrically separate the first edge connector pin from the second edge connector pin. 2. The method of claim 1 , wherein removing the at least a portion of the electrical bridging element comprises performing a mechanical drilling operation on the electrical bridging element. 3. The method of claim 1 , wherein the first conductive layer for the first edge connector pin, the second edge connector pin, and the electrical bridging element are formed on a same surface of the substrate. 4. The method of claim 1 , wherein electroplating the second conductive layer onto both the first conductive layer for the first edge connector pin and the first conductive layer for the second edge connector pin comprises applying a plating bias to both the first edge connector pin and the second edge connector pin via the plating current conductor. 5. The method of claim 1 , wherein at least a portion of the plating current conductor is disposed outside a perimeter of the printed circuit board. 6. The method of claim 1 , wherein the first edge connector pin is configured as a non-signal-carrying connector pin, and the second edge connector pin is configured as a signal-carrying connector pin. 7. The method of claim 6 , wherein a first conductive layer for the plating current conductor is coupled directly to the first conductive layer for the first edge connector pin and is coupled indirectly to the first conductive layer for the second edge connector pin. 8. The method of claim 6 , wherein a first conductive layer of the plating current conductor is electrically coupled to the first conductive layer for the first edge connector pin via a ground plane of the printed circuit board. 9. The method of claim 6 , wherein a first conductive layer for the first edge connector pin is electrically coupled to a ground plane of the printed circuit board by at least one via of the printed circuit board. 10. The method of claim 6 , wherein forming the first conductive layer for the first edge connector pin on the substrate comprises concurrently forming a ground plane of the printed circuit board. 11. The method of claim 1 , wherein forming the first conductive layer for the first edge connector pin on the substrate comprises concurrently forming a first conductive layer for the electrical bridging element and a first conductive layer for the plating current conductor. 12. The method of claim 1 , wherein electrically separating the first edge connector pin from the second edge connector pin is performed after electroplating the second layer onto the first conductive layer of the first edge connector pin and the first conductive layer of the second edge connector pin.

Assignees

Inventors

Classifications

  • Drilling of holes · CPC title

  • Pads along the edge of rigid circuit boards, e.g. for pluggable connectors · CPC title

  • H05K3/242Primary

    characterised by using temporary conductors on the printed circuit for electrically connecting areas which are to be electroplated · CPC title

  • Configurations of connections suitable for easy deletion, e.g. modifiable circuits or temporary conductors for electroplating; Processes for deleting connections · CPC title

  • Overplating, e.g. for reinforcing conductors or bumps; Plating over filled vias · CPC title

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Frequently asked questions

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What does patent US11653455B2 cover?
A method for forming a printed circuit board includes: forming on a substrate a first conductive layer for a first edge connector pin and a first conductive layer for a second edge connector pin, wherein the first conductive layer for the first edge connector pin and the first conductive layer for the second edge connector pin are electrically coupled to one another via a first conductive layer…
Who is the assignee on this patent?
Nvidia Corp
What technology area does this patent fall under?
Primary CPC classification H05K3/242. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue May 16 2023 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).