Intermediate separation layers at the back-end-of-line

Patent metadata

Field	Value
Publication number	US-11652047-B2
Application number	US-201916457641-A
Country	US
Kind code	B2
Filing date	Jun 28, 2019
Priority date	Jun 28, 2019
Publication date	May 16, 2023
Grant date	May 16, 2023

Abstract

Embodiments herein describe techniques for a semiconductor device having an interconnect structure including an inter-level dielectric (ILD) layer between a first layer and a second layer of the interconnect structure. The interconnect structure further includes a separation layer within the ILD layer. The ILD layer includes a first area with a first height to extend from a first surface of the ILD layer to a second surface of the ILD layer. The ILD layer further includes a second area with a second height to extend from the first surface of the ILD layer to a surface of the separation layer, where the first height is larger than the second height. Other embodiments may be described and/or claimed.

First claim

What is claimed is:

1. A semiconductor device, comprising:
an interconnect structure above a substrate, wherein the interconnect structure includes:
an inter-level dielectric (ILD) layer between a first layer and a second layer, wherein the ILD layer has a first surface adjacent to the first layer, and a second surface adjacent to the second layer, a first height measured vertically between the first surface and the second surface, and a length of the ILD layer measured horizontally in parallel with a surface of the substrate;
a separation layer within the ILD layer, wherein the separation layer has a first surface opposite to the first surface of the ILD layer, and a second surface opposite to the second surface of the ILD layer, and wherein the ILD layer includes a first area with the first height to extend from the first surface of the ILD layer to the second surface of the ILD layer, a second area with a second height to extend from the first surface of the ILD layer to the first surface of the separation layer, and wherein the first height is larger than the second height.

2. The semiconductor device of claim 1 , wherein the separation layer has a length measured horizontally in parallel with the surface of the substrate that is shorter than the length of the ILD layer.

3. The semiconductor device of claim 1 , wherein the separation layer is a first separation layer, and the first layer or the second layer is a second separation layer that extends horizontally with a length substantially same as the length of the ILD layer.

4. The semiconductor device of claim 1 , wherein the first layer or the second layer is a metal layer, or another ILD layer.

5. The semiconductor device of claim 1 , wherein the second area of the ILD layer includes a transistor, a capacitor, a diode, a resistor, an inductor, a fuse, a transformer, or a sensor.

6. The semiconductor device of claim 1 , wherein the second area of the ILD layer includes a thin film transistor having a channel layer, and wherein the channel layer includes a material selected from the group consisting of CuS 2 , CuSe 2 , WSe 2 , indium doped zinc oxide (IZO), zinc tin oxide (ZTO), amorphous silicon (a-Si), amorphous germanium (a-Ge), low-temperature polycrystalline silicon (LTPS), transition metal dichalcogenide (TMD), yttrium-doped zinc oxide (YZO), polysilicon, poly germanium doped with boron, poly germanium doped with aluminum, poly germanium doped with phosphorous, poly germanium doped with arsenic, indium oxide, tin oxide, zinc oxide, gallium oxide, indium gallium zinc oxide (IGZO), copper oxide, nickel oxide, cobalt oxide, indium tin oxide, tungsten disulphide, molybdenum disulphide, molybdenum selenide, black phosphorus, indium antimonide, graphene, graphyne, borophene, germanene, silicene, Si 2 BN, stanene, phosphorene, molybdenite, poly-III-V like InAs, InGaAs, InP, amorphous InGaZnO (a-IGZO), crystal-like InGaZnO (c-IGZO), GaZnON, ZnON, or C-Axis Aligned Crystal (CAAC), molybdenum and sulfur, and a group-VI transition metal dichalcogenide.

7. The semiconductor device of claim 6 , wherein the ILD layer includes a third area with a third height to extend from the second surface of the separation layer to the second surface of the ILD layer, and vertically aligned with the second area, and wherein the first height is larger than the third height.

8. The semiconductor device of claim 7 , further comprising a first via through the first area, and a second via through the third area, wherein the second via is shorter than the first via.

9. The semiconductor device of claim 1 , wherein the substrate includes a material selected from the group consisting of a silicon substrate, a glass substrate, a metal substrate, and a plastic substrate.

10. The semiconductor device of claim 1 , wherein the ILD layer includes a material selected from the group consisting of silicon dioxide (SiO 2 ), carbon doped oxide (CDO), silicon nitride, perfluorocyclobutane, polytetrafluoroethylene, fluorosilicate glass (FSG), organic polymer, silsesquioxane, siloxane, and organosilicate glass.

11. The semiconductor device of claim 1 , wherein the separation layer includes one or more of an etching stop layer, a barrier layer, a capping layer, or a hard mask layer.

12. The semiconductor device of claim 1 , wherein the separation layer includes an etching stop layer, and the etching stop layer includes boron doped Si, boron doped Ge, boron doped SiGe, phosphorus doped Si, phosphorus doped Ge, or phosphorus doped SiGe.

13. The semiconductor device of claim 1 , wherein the interconnect structure further includes a sealant layer above, below, or adjacent to the separation layer.

14. The semiconductor device of claim 1 , wherein the first layer is another separation layer, the ILD layer is a first ILD layer, and the semiconductor device further includes a second ILD layer separated from the first ILD layer by the first layer.

15. A computing device, comprising:
a circuit board; and
a memory device coupled to the circuit board and including a memory array, wherein the memory array includes a plurality of memory cells, a memory cell of the plurality of memory cells includes a transistor coupled to a capacitor formed within an inter-level dielectric (ILD) layer including a dielectric material above a first layer and a substrate;
wherein the transistor includes a gate electrode; a channel layer including a channel material, separated from the gate electrode by a gate dielectric layer; and a source electrode and a drain electrode above the channel layer, and wherein the gate electrode, the channel layer, the source electrode and the drain electrode are above the first layer and below a separation layer;
wherein the capacitor is above the separation layer and below a second layer, and wherein the ILD layer includes a first area with a first height to extend from a first surface of the ILD layer to a second surface of the ILD layer between the first layer and the second layer, and a second area with a second height to extend between the first layer and the separation layer, and wherein the first height is larger than the second height; and
wherein the drain electrode of the transistor is coupled to a bottom plate of the capacitor through the separation layer, a top plate of the capacitor is coupled to a source line of the memory array, and the gate electrode of the transistor is coupled to a word line of the memory array.

16. The computing device of claim 15 , wherein the first layer or the second layer is a metal layer, or another ILD layer.

17. The computing device of claim 15 , wherein the channel layer of the transistor includes a material selected from the group consisting of CuS 2 , CuSe 2 , WSe 2 , indium doped zinc oxide (IZO), zinc tin oxide (ZTO), amorphous silicon (a-Si), amorphous germanium (a-Ge), low-temperature polycrystalline silicon (LTPS), transition metal dichalcogenide (TMD), yttrium-doped zinc oxide (YZO), polysilicon, poly germanium doped with boron, poly germanium doped with aluminum, poly germanium doped with phosphorous, poly germanium doped with arsenic, indium oxide, tin oxide, zinc oxide, gallium oxide, indium gallium zinc oxide (IGZO), copper oxide, nickel oxide, cobalt oxide, indium tin oxide, tungsten disulphide, molybdenum disulphide, molybdenum selenide, black phosphorus, indium antimonide, graphene, graphyne, borophene, germanene, silicene, Si 2 BN, stanene, phosphorene, molybdenite, poly-III-V like InAs, InGaAs, InP, amorphous InGaZnO (a-IGZO), crystal-like InGaZnO (c-IGZO), GaZnON, ZnON, or C-Axis Aligned Crystal (CAAC), molybdenum and

Assignees

• Intel Corp

Inventors

• Lajoie Travis W
• Sharma Abhishek A
• Le Van H
• Ku Chieh-Jen
• Wang Pei-Hua
• Kavalieros Jack T
• Sell Bernhard
• Ghani Tahir
• George Gregory
• Garg Akash
• Rollins Julie
• Gardiner Allen B
• Ogadhoh Shem
• Alzate Vinasco Juan G
• Arslan Umut
• Hamzaoglu Fatih
• Mehta Nikhil
• Chen Ting
• Hadagali Vinaykumar V

Classifications

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/074

  of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers · CPC title

• H10W20/43 Primary

  Layouts of interconnections · CPC title

• H10W20/47 Primary

  comprising two or more dielectric layers having different properties, e.g. different dielectric constants · CPC title

• H10D84/813

  Combinations of field-effect devices and capacitor only · CPC title