Multiple mode arithmetic circuit

Patent metadata

Field	Value
Publication number	US-11650792-B2
Application number	US-202217569801-A
Country	US
Kind code	B2
Filing date	Jan 6, 2022
Priority date	Aug 8, 2019
Publication date	May 16, 2023
Grant date	May 16, 2023

Abstract

A tile of an FPGA includes a multiple mode arithmetic circuit. The multiple mode arithmetic circuit is configured by control signals to operate in an integer mode, a floating-point mode, or both. In some example embodiments, multiple integer modes (e.g., unsigned, two's complement, and sign-magnitude) are selectable, multiple floating-point modes (e.g., 16-bit mantissa and 8-bit sign, 8-bit mantissa and 6-bit sign, and 6-bit mantissa and 6-bit sign) are supported, or any suitable combination thereof. The tile may also fuse a memory circuit with the arithmetic circuits. Connections directly between multiple instances of the tile are also available, allowing multiple tiles to be treated as larger memories or arithmetic circuits. By using these connections, referred to as cascade inputs and outputs, the input and output bandwidth of the arithmetic circuit is further increased.

First claim

What is claimed is:

1. A circuit comprising:
a mode selection input that selects a mode from a set of modes comprising a first mode, a second mode, and a third mode; and
a plurality of integer arithmetic logic blocks;
wherein:
in the first mode, the plurality of integer arithmetic logic blocks is configured to perform a first number of operations on first integer operands of a first size;
in the second mode, the plurality of integer arithmetic logic blocks is configured to perform operations on floating-point operands; and
in the third mode, the plurality of integer arithmetic logic blocks is configured to perform a second number of operations on second integer operands of a second size, the second size being larger than the first size, the second number of operations being smaller than the first number of operations.

2. The circuit of claim 1 , further comprising:
a set of input connections; and
bit remapping circuitry that selectively connects the input connections to the integer arithmetic logic blocks based on the mode selection input, the bit remapping circuitry being operable in both the first mode and the second mode.

3. The circuit of claim 2 , further comprising:
interconnection circuitry among the plurality of integer arithmetic logic blocks, the interconnection circuitry comprising a plurality of registers and multiplexers, the registers and multiplexers being operable in both the first mode and the second mode.

4. The circuit of claim 1 , wherein, in the second mode:
the floating-point operands comprise a third operand and a fourth operand; and
the plurality of integer arithmetic logic blocks is further configured to shift a mantissa of the fourth operand by a difference between an exponent of the third operand and an exponent of the fourth operand based on a determination that the exponent of the third operand is the greatest exponent among exponents of the floating-point operands.

5. The circuit of claim 1 , wherein:
the floating-point operands are first floating-point operands of a first format;
the set of modes further comprises a fourth mode;
in the second mode, the plurality of integer arithmetic logic blocks is further configured to convert the first floating-point operands to a third format; and
in the fourth mode, the plurality of integer arithmetic logic blocks is configured to:
perform operations on second floating-point operands of a second format; and
convert the second floating-point operands to the third format.

6. The circuit of claim 5 , wherein the third format comprises a fifteen-bit mantissa, a one-bit sign, and an eight-bit exponent.

7. The circuit of claim 5 , wherein:
a mantissa size of the third format is greater than or equal to a mantissa size of the first format;
the mantissa size of the third format is greater than or equal to a mantissa size of the second format; and
the mantissa size of the second format is different from the mantissa size of the first format.

8. The circuit of claim 1 , further comprising:
an adder that generates a result that is a sum of partial products.

9. The circuit of claim 1 , wherein:
the first size is eight bits;
the second size is sixteen bits; and
the first number of operations is four times the second number of operations.

10. The circuit of claim 1 , further comprising:
a plurality of output connections that, in the first mode and the second mode, provide a plurality of partial products, wherein a bit width of each partial product is based on a number of partial products provided.

11. The circuit of claim 1 , wherein:
the first integer operands of the first size are eight-bit integers; and
the second integer operands of the second size are sixteen-bit integers.

12. The circuit of claim 1 , wherein:
the second size is twice the first size; and
the first number of operations is twice the second number of operations.

13. The circuit of claim 1 , further comprising:
a plurality of output connections that, in the first mode and the second mode, provide a plurality of partial products, wherein a bit width of each partial product is based on a number of partial products provided.

14. A non-transitory machine-readable medium containing instructions that, when executed by one or more processors, cause the one or more processors to control configuration of a field programmable gate array (FPGA) comprising:
a mode selection input that selects a mode from a set of modes comprising a first mode, a second mode, and a third mode; and
a plurality of integer arithmetic logic blocks;
wherein:
in the first mode, the plurality of integer arithmetic logic blocks is configured to perform a first number of operations on first integer operands of a first size;
in the second mode, the plurality of integer arithmetic logic blocks is configured to perform operations on floating-point operands; and
in the third mode, the plurality of integer arithmetic logic blocks is configured to perform a second number of operations on second integer operands of a second size, the second size being larger than the first size, the second number of operations being smaller than the first number of operations.

15. The non-transitory machine-readable medium of claim 14 , wherein the FPGA further comprises:
a set of input connections; and
bit remapping circuitry that selectively connects the input connections to the integer arithmetic logic blocks based on the mode selection input, the bit remapping circuitry being operable in both the first mode and the second mode.

16. The non-transitory machine-readable medium of claim 15 wherein the FPGA further comprises:
interconnection circuitry among the plurality of integer arithmetic logic blocks, the interconnection circuitry comprising a plurality of registers and multiplexers, the registers and multiplexers being operable in both the first mode and the second mode.

17. The non-transitory machine-readable medium of claim 14 , wherein:
the floating-point operands are first floating-point operands of a first format;
the set of modes further comprises a fourth mode;
in the second mode, the plurality of integer arithmetic logic blocks is further configured to convert the first floating-point operands to a third format; and
in the fourth mode, the plurality of integer arithmetic logic blocks is configured to:
perform operations on second floating-point operands of a second format; and
convert the second floating-point operands to the third format.

18. The non-transitory machine-readable medium of claim 17 , wherein the third format comprises a fifteen-bit mantissa, a one-bit sign, and an eight-bit exponent.

19. A method comprising:
receiving, by a circuit, a first mode selection input that selects a first mode from a set of modes comprising the first mode, a second mode, and a third mode;
in response to receiving the first mode selection input, configuring a plurality of integer arithmetic logic blocks to perform a first number of operations on first integer operands of a first size;
receiving, by the circuit, a second mode selection input that selects the second mode from the set of modes;
in response to receiving the second mode selection input, configuring the plurality of integer arithmetic logic blocks to perform operations on floating-point operands;
receiving, by the circuit, a third mode selection input that selects the third mode from the set of modes; and
in response to receiving the third mode selection input, configuring the plurality of integer arithmetic logic blocks

Assignees

• Achronix Semiconductor Corp

Inventors

• Pugh Daniel
• Nijssen Raymond
• Fitton Michael Philip
• Van Der Goot Marcel

Classifications

• G06F7/5324

  partitioned, i.e. using repetitively a smaller parallel parallel multiplier or using an array of such smaller multipliers · CPC title

• G06F7/5443

  Sum of products (for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00) · CPC title

• G06F7/4876 Primary

  Multiplying · CPC title

• G06F2207/3824

  Accepting both fixed-point and floating-point numbers · CPC title

• G06F7/49915 Primary

  Mantissa overflow or underflow in handling floating-point numbers · CPC title