Solid state drive multi-card adapter with integrated processing

Patent metadata

Field	Value
Publication number	US-11650764-B2
Application number	US-202117206106-A
Country	US
Kind code	B2
Filing date	Mar 18, 2021
Priority date	Mar 2, 2015
Publication date	May 16, 2023
Grant date	May 16, 2023

Abstract

Embodiments of the inventive concept include solid state drive (SSD) multi-card adapters that can include multiple solid state drive cards, which can be incorporated into existing enterprise servers without major architectural changes, thereby enabling the server industry ecosystem to easily integrate evolving solid state drive technologies into servers. The SSD multi-card adapters can include an interface section between various solid state drive cards and drive connector types. The interface section can perform protocol translation, packet switching and routing, data encryption, data compression, management information aggregation, virtualization, and other functions.

First claim

What is claimed is:

1. A device, comprising:
a first connector configured to support a storage communication protocol;
an interface section coupled to the first connector;
two or more second connectors coupled to the interface section, the two or more second connectors being configured to support at least a first storage protocol and a second storage protocol different from the first storage protocol; and
a compute resource including a field programmable gate array (FPGA) in communication with and connected to one or more solid state storage devices and the interface section,
wherein at least one of the interface section or the one or more solid state storage devices is configured to offload at least one operation in association with storing data onto the one or more solid state storage devices, to the compute resource such that the compute resource is configured to perform a first operation from among data encryption, data protection, data compression, or data deduplication on the data configured for storage onto the one or more solid state storage devices at a first period, and wherein the FPGA of the compute resource is configured to be reconfigured, and to perform a second reconfigured operation different from the first operation from among the data encryption, the data protection, the data compression, or the data deduplication on the data configured for storage onto the one or more solid state storage devices at a second period.

2. The device of claim 1 , wherein at least one of the interface section or the one or more solid state storage devices is configured to offload at least one operation in association with reading data from the one or more solid state storage devices, to the compute resource such that the compute resource performs one or more operations associated with at least one of data encryption, data protection, data decompression, or data deduplication on the data configured to be read from the one or more solid state storage devices.

3. The device of claim 2 , wherein the one or more solid state storage devices, the interface section, the two or more second connectors and the compute resource are enclosed within a same enclosure configured for connection via the first connector to a computing device.

4. The device of claim 1 , wherein the interface section and the two or more second connectors are on a same surface of a circuit board.

5. The device of claim 1 , wherein at least one of the first storage protocol or the second storage protocol include at least one of an Ethernet protocol, a serial ATA (SATA) protocol or a peripheral component interconnect express (PCIe) protocol.

6. The device of claim 1 , wherein the interface section is accessible to a host device via an enclosure-specific protocol, the enclosure-specific protocol including at least one of an Ethernet protocol, a SATA protocol or a PCIe protocol.

7. The device of claim 1 , further comprising one or more thermal sensors configured to provide thermal data, wherein the compute resource is configured to communicate with at least one memory unit using the one or more storage protocols.

8. The device of claim 1 , wherein the compute resource is configured to aggregate management information, wherein the aggregated management information includes the thermal data, and wherein the interface section is configured to communicate the aggregated management information in at least one of an out-of-band fashion or an in-band fashion.

9. The device of claim 1 , wherein the interface section includes at least one of a PCIe switch, a PCIe hub, a PCIe bus, an Ethernet switch, an Infiniband switch, a Fibre Channel switch, or other communication fabric component.

10. The device of claim 1 , wherein the device is configured to be seated within one of a plurality of slots of a host device.

11. The device of claim 1 , further comprising one or more memory elements, wherein the device is configured to present the one or more memory elements as a single virtualized device.

12. A device, comprising:
a first connector configured to support a storage communication protocol;
an interface section including a field programmable gate array (FPGA) coupled to the first connector; and
two or more second connectors coupled to the interface section, the two or more second connectors being configured to support at least a first storage protocol and a second storage protocol different from the first storage protocol,
wherein the interface section is in communication with and connected to one or more solid state storage devices;
wherein at least one of the interface section or the one or more solid state storage devices is configured to offload at least one operation in association with storing data onto the one or more solid state storage devices, to the interface section such that the interface section is configured to perform a first operation from among data encryption, data protection, data compression, or data deduplication on the data configured for storage onto the one or more solid state storage devices at a first period, and wherein the FPGA of the interface section is configured to be reconfigured, and to perform a second reconfigured operation different from the first operation from among the data encryption, the data protection, the data compression, or the data deduplication on the data configured for storage onto the one or more solid state storage devices at a second period.

13. The device of claim 12 , wherein at least one of the interface section or the one or more solid state storage devices is configured to offload at least one operation in association with reading data from the one or more solid state storage devices, to the interface section such that the interface section performs at least one of data encryption, data protection, data decompression, or data deduplication on the data configured to be read from the one or more solid state storage devices.

14. The device of claim 13 , wherein the one or more solid state storage devices, the interface section, and the two or more second connectors are enclosed within a same enclosure configured for connection via the first connector to a computing device.

15. The device of claim 12 , wherein the interface section comprises a compute resource, the compute resource being configured to:
perform one or more operations associated with the at least one of the data encryption, the data protection, the data decompression, or the data deduplication on the data configured to be read from the one or more solid state storage devices; and
perform the at least one of the data encryption, the data protection, the data compression, or the data deduplication on the data configured for storage onto the one or more solid state storage devices.

16. The device of claim 15 , further comprising one or more thermal sensors configured to provide thermal data, wherein the compute resource is configured to communicate with at least one memory unit using the one or more storage protocols.

17. The device of claim 15 , wherein the compute resource is configured to aggregate management information, wherein the aggregated management information includes the thermal data, and wherein the interface section is configured to communicate the aggregated management information in at least one of an out-of-band fashion or an in-band fashion.

18. The device of claim 12 , wherein the interface section and the two or more second connectors are on a same surface of a circuit board.

19. The device of claim 12 , wherein at least one of the first storage protocol or t

Assignees

• Samsung Electronics Co Ltd

Inventors

• WORLEY Fred
• Rogers Harry
• Marripudi Gunneswara
• Ping Zhan
• Sinha Vikas

Classifications

• G06F2213/0026

  PCI express · CPC title

• G06F3/0661 Primary

  Format or protocol conversion arrangements · CPC title

• G06F2213/0032

  Serial ATA [SATA] · CPC title

• G06F3/0688

  Non-volatile semiconductor memory arrays · CPC title

• G06F3/0613

  in relation to throughput · CPC title