Nonvolatile tunable capacitive processing unit

Patent metadata

Field	Value
Publication number	US-11647684-B2
Application number	US-202117216937-A
Country	US
Kind code	B2
Filing date	Mar 30, 2021
Priority date	Mar 30, 2021
Publication date	May 9, 2023
Grant date	May 9, 2023

Abstract

In an approach for forming a nonvolatile tunable capacitor device, a first electrode layer is formed distally opposed from a second electrode layer, the first electrode layer configured to make a first electrical connection and the second electrode layer configured to make a second electrical connection. A dielectric layer is posited between the first electrode layer and adjacent to the second electrode layer. A phase change material (PCM) layer is posited between the first electrode layer and the second electrode layer adjacent to the dielectric layer. An energizing component is provided to heat the PCM layer to change a phase of the PCM layer. The energizing component may include a heating element or electrical probe in direct contact with the PCM layer, that when energized is configured to apply heat to the PCM layer. The phase of the PCM layer is changeable between an amorphous phase and a crystalline phase.

First claim

What is claimed is:

1. A method of performing a multiply-accumulate (MAC) operation for a neural network (NN), the method comprising:
providing one or more circuit configurations, wherein the one or more circuit configurations comprise:
a charging transistor comprising:
a first charging transistor terminal connected to a voltage line; and
a second charging transistor terminal connected to a first capacitor terminal of a tunable capacitor, wherein the tunable capacitor comprises a second capacitor terminal connected to a ground terminal;

a discharging transistor comprising:
a first discharging terminal connected to the second charging transistor terminal and the first capacitor terminal; and
a second discharging terminal connected to a current line;

providing a predefined amount of heat to the tunable capacitor for a predefined amount of time, wherein the tunable capacitor has a first capacitance value and the predefined amount of heat is sufficient to change the first capacitance value to a second capacitance value;
charging the tunable capacitor for a first predefined amount of time by applying an input voltage to the tunable capacitor via the charging transistor in a closed state and the discharging transistor in an open state;
discharging the tunable capacitor for a second predefined amount of time by stopping the input voltage to the tunable capacitor via the charging transistor in the open state and the discharging transistor in the closed state, wherein charges flow from the tunable capacitor through the discharging transistor to an integrator circuit;
determining a total charge of the one or more circuit configurations comprising the tunable capacitor by integrating the charges of the one or more circuit configurations through the discharging transistor using the integrator circuit; and
generating a result for the MAC operation based, at least in part, on the total charge of the one or more circuit configurations.

2. The method of claim 1 , wherein providing the predefined amount of heat is configured to set the tunable capacitor to a weight of the NN represented as the second capacitance value.

3. The method of claim 1 , further comprising:
determining the predefined amount of heat as a temperature change sufficient to achieve a desired weight corresponding to the second capacitance value.

4. The method of claim 1 , wherein a phase of a PCM layer of the tunable capacitor is selectively changeable between an amorphous phase corresponding to a resistive PCM layer to a crystalline phase corresponding to a conductive PCM layer.

5. The method of claim 1 , wherein a PCM layer of the tunable capacitor comprises a composition of one of Ge 2 Sb 2 Te 5 , GeTe, and Sb 2 Te 3 .

6. The method of claim 1 , wherein a dielectric layer of the tunable capacitor comprises a composition of HfO 2 .

Assignees

• IBM

Inventors

• Cohen Guy M
• Ando Takashi
• Gong Nanbo
• Li Yulong

Classifications

• H10D1/684

  the dielectrics comprising multiple layers, e.g. comprising buffer layers, seed layers or gradient layers · CPC title

• H10N70/8828 Primary

  Tellurides, e.g. GeSbTe · CPC title

• G11C13/0004

  comprising amorphous/crystalline phase transition cells · CPC title

• H10N70/8833

  Binary metal oxides, e.g. TaOx · CPC title

• H10N70/8413

  adapted for resistive heating · CPC title