Apparatuses and methods for fuse error detection

Patent metadata

Field	Value
Publication number	US-11645134-B2
Application number	US-201916545721-A
Country	US
Kind code	B2
Filing date	Aug 20, 2019
Priority date	Aug 20, 2019
Publication date	May 9, 2023
Grant date	May 9, 2023

Abstract

An example fuse error detection circuit configured to receive a first data set from a fuse array during a first fuse data broadcast and to encode the first data set to provide first signature data. The fuse error detection circuit is further configured to receive a second data set from the fuse array during a second fuse data broadcast and to encode the second data set to provide second signature data. The fuse error detection circuit is further configured to compare the first signature data and the second signature data and to provide a match indication having a value based on the comparison between the first signature data and the second signature data.

First claim

What is claimed is:

1. An apparatus comprising:
a fuse error detection circuit configured to receive a first data set from a fuse array during a first fuse data broadcast, wherein the first data set is based at least in part on data programmed in the fuse array, and to encode the first data set based at least in part on current signature data and the received first data set to provide first signature data, wherein the fuse error detection circuit is further configured to receive a second data set from the fuse array during a second fuse data broadcast, wherein the second data set is based at least in part on data programmed in the fuse array, and to encode the second data set based at least in part on the first signature data and the received second data set to provide second signature data, wherein the fuse error detection circuit is further configured to compare the first signature data and the second signature data and to provide a match indication having a value based on the comparison between the first signature data and the second signature data.

2. The apparatus of claim 1 , wherein the fuse error detection circuit includes a signature register configured to receive the first data set and to encode the first data set to provide the first signature data.

3. The apparatus of claim 2 , wherein the signature register is a multiple-input signature register configured to iteratively receive and encode respective subsets of the first data set to provide the first signature data, wherein the first signature data includes fewer bits than the first data set.

4. The apparatus of claim 2 , wherein the signature register is further configured to receive the second data set and to encode the second data set to provide the second signature data.

5. The apparatus of claim 2 , wherein the fuse error detection circuit includes a storage register configured to receive the first signature data from the signature register and to store the first signature data during the second fuse data broadcast.

6. The apparatus of claim 5 , wherein the storage register is a shift register.

7. The apparatus of claim 2 , wherein the fuse error detection circuit includes a control circuit configured to cause the signature register to latch the first data set in response to a selection signal provided during the first fuse data broadcast.

8. The apparatus of claim 7 , wherein the control circuit is further configured to cause the first signature data to latch at a storage register in response to transition of a token reset signal received between the first fuse data broadcast and the second fuse data broadcast.

9. The apparatus of claim 1 , wherein the fuse error detection circuit further includes a comparator circuit configured to compare the first signature data and the second signature data to provide comparison results, wherein the comparator is configured to latch the value of the match indication based on the comparison results.

10. The apparatus of claim 9 , wherein the comparator circuit uses bitwise XOR logic to perform the comparison between the first signature data and the second signature data.

11. The apparatus of claim 1 , wherein the fuse error detection circuit includes:
a first register configured to, during the first fuse data broadcast, receive the first data set and to encode the first data set to provide the first signature data in response to a first clock signal, wherein the first register is further configured to, during the second fuse data broadcast, receive the second data set and to encode the second data set to provide the second signature data in response to the first clock signal;
a second register configured to latch the first signature data from the first register in response to a second clock signal; and
a comparator configured to compare the first signature data and the second signature data to provide comparison results, wherein the comparator is configured to latch the value of the match indication based on the comparison results in response to a third clock signal.

12. The apparatus of claim 1 , further comprising the fuse array having a set of fuses, wherein the first data set and the second data set are both read from the set of fuses.

13. The apparatus of claim 12 , further comprising a fuse logic configured to read the set of fuses of the fuse array during the first and second fuse data broadcasts to provide the first data set and the second data set, respectively.

14. The apparatus of claim 1 , wherein the first signature data is updated relative to the current signature data, and wherein the first signature data is indicative of a value of an entirety of the first data set or a subset of values of the first data set.

15. A method comprising:
receiving, at a fuse error detection circuit of a semiconductor device, a first data set from a fuse array during a first fuse data broadcast, wherein the first data set is based at least in part on data programmed in the fuse array;
encoding the first data set based at least in part on current signature data and the received first data set to provide first signature data;
receiving, at the fuse error detection circuit, a second data set from the fuse array during a second fuse data broadcast, wherein the second data set is based at least in part on data programmed in the fuse array;
encoding the second data set based at least in part on the first signature data and the received second data set to provide second signature data;
comparing the first signature data and the second signature data; and
providing a match indication haying a value based on the comparison between the first signature data and the second signature data.

16. The method of claim 15 , further comprising encoding the first data set via a signature register.

17. The method of claim 15 , further comprising:
serially receiving subsets of the first data set; and
updating the first signature data based on each received subset of the first data set.

18. The method of claim 15 , wherein the first signature data includes fewer bits than the first data set.

19. The method of claim 15 , further comprising storing the first signature data prior to receipt of the second fuse data set.

20. The method of claim 15 , further comprising, in response to the match indication indicating a mismatch between the first signature data and the second signature data, causing a third fuse data broadcast.

21. The method of claim 15 , further comprising, in response to the match indication indicating a mismatch between the first signature data and the second signature data, causing the semiconductor device to suspend operation.

Assignees

• Micron Technology Inc

Inventors

• Miller Daniel S
• Werhane Kevin G
• Fujiwara Yoshinori
• Wieduwilt Christopher G
• Johnson Jason M
• Someya Minoru

Classifications

• G11C16/22

  Safety or protection circuits preventing unauthorised or accidental access to memory cells · CPC title

• G06F11/0772

  Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers · CPC title

• G06F11/073

  in a memory management context, e.g. virtual memory or cache management (memory management G06F12/00; testing of static memory units G11C29/00) · CPC title

• G11C29/787

  using a fuse hierarchy · CPC title

• G06F11/0727

  in a storage system, e.g. in a DASD or network based storage system (drivers for digital recording or reproducing units G06F3/06; circuits for error detection or correction within digital recording or reproducing units G11B20/18; for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS], H04L67/1097) · CPC title