Method for producing a semiconductor wafer composed of monocrystalline silicon

Patent metadata

Field	Value
Publication number	US-11639558-B2
Application number	US-202217859017-A
Country	US
Kind code	B2
Filing date	Jul 7, 2022
Priority date	Oct 26, 2017
Publication date	May 2, 2023
Grant date	May 2, 2023

Abstract

A method produces a single-crystal silicon semiconductor wafer. A single-crystal silicon substrate wafer is double side polished. A front side of the substrate wafer is chemical mechanical polished (CMP). An epitaxial layer of single-crystal silicon is deposited on the front side of the substrate wafer. A first rapid thermal anneal (RTA) treatment is performed on the coated substrate wafer at 1275-1295° C. for 15-30 seconds in argon and oxygen, having oxygen of 0.5-2.0 vol %. The coated substrate wafer is then cooled at or below 800° C., with 100 vol % argon. A second RTA treatment is performed on the coated substrate wafer at a 1280-1300° C. for 20-35 seconds in argon. An oxide layer is removed from a front side of the coated substrate wafer. The front side of the coated substrate wafer is polished by CMP.

First claim

What is claimed is:

1. A method for producing a semiconductor wafer of single-crystal silicon, the method comprising:
providing a substrate wafer of single-crystal silicon;
polishing the substrate wafer by double side polishing (DSP);
polishing a front side of the substrate wafer by chemical mechanical polishing (CMP);
depositing at least one epitaxial layer of single-crystal silicon on the front side of the substrate wafer creating a coated substrate wafer;
loading a rapid thermal anneal (RTA) reactor with the coated substrate wafer;
performing a first RTA treatment of the coated substrate wafer at a temperature in a temperature range of not less than 1275° C. and not more than 1295° C. for a period of not less than 15 seconds and not more than 30 seconds in an atmosphere consisting of argon and oxygen having a proportion of oxygen of not less than 0.5 vol % and not more than 2 vol %;
cooling the coated substrate wafer after the first RTA treatment to a temperature of not more than 800° C., wherein a gas feed to the coated substrate wafer is set to 100 vol % argon;
performing a second RTA treatment of the coated substrate wafer at a temperature in a temperature range of not less than 1280° C. and not more than 1300° C. for a period of not less than 20 seconds and not more than 35 seconds in an atmosphere consisting of argon;
removing an oxide layer from a front side of the coated substrate wafer; and
polishing the front side of the coated substrate wafer by CMP.

2. The method according to claim 1 , wherein the oxide layer is removed by treating the coated substrate wafer with aqueous HF solution.

3. The method according to claim 1 , wherein 100 vol % of oxygen is passed through the RTA reactor prior to the first RTA treatment.

4. The method according to claim 1 , wherein the produced semiconductor wafer of single-crystal silicon has the front side polished and a back side polished, has a denuded zone, which extends from the polished front side toward the polished back side to a depth of not less than 30 μm, and has a region adjacent to the denuded zone and including (bulk micro defects) BMD nuclei, a density of the BMDs at a distance of 120 μm from the polished front side being not less than 2×108 cm-3.

5. The method of claim 1 , wherein the at least one epitaxial layer has a thickness of not less than 1 μm and not more than 5 μm, with n/n-doping or p/p-doping, a dopant of an n-type being phosphorous and a dopant of a p-type is being boron.

6. The method according to claim 1 , wherein the produced semiconductor wafer of single-crystal silicon has a density of developed BMDs that decreases from a peak density in a direction of a central plane.

Assignees

• Siltronic Ag

Inventors

• Mueller Timo
• Boy Michael
• Gehmlich Michael
• Sattler Andreas

Classifications

• H10P52/402

  of semiconductor materials · CPC title

• H10P36/20 Primary

  Intrinsic gettering, i.e. thermally inducing defects by using oxygen present in the silicon body · CPC title

• H10P36/07

  of silicon-on-insulator structures · CPC title

• H10D62/83

  being Group IV materials, e.g. B-doped Si or undoped Ge · CPC title

• H10D62/57

  the imperfections being on the surface of the semiconductor body, e.g. the body having a roughened surface · CPC title