Metal oxide semiconductor-controlled thyristor device having uniform turn-off characteristic and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-11637192-B2
Application number	US-202117355977-A
Country	US
Kind code	B2
Filing date	Jun 23, 2021
Priority date	Jun 24, 2020
Publication date	Apr 25, 2023
Grant date	Apr 25, 2023

Abstract

The present invention forms an off-FET channel having a uniform and short length by using a self-align process of a method of forming and recessing a spacer, thereby enhancing the current driving capability of an off-FET and the uniformity of a device operation.

First claim

What is claimed is:

1. A method of manufacturing a metal oxide semiconductor (MOS)-controlled thyristor (MCT) device, the method comprising:
forming a first conductive type base region doped with first conductive type impurities and a second conductive type emitter region doped with second conductive type impurities in the first conductive type base region, in a substrate;
forming a spacer on a side surface of an oxide layer which is formed on the substrate and upward exposes the second conductive type emitter region;
ion-implanting the first conductive type impurities into the second conductive type emitter region upward exposed by the spacer to form a first conductive type drain region of an off-field effect transistor (TFT) and to form a channel region of the off-FET defined between a junction surface of the second conductive type emitter region and a junction surface of the first conductive type drain region;
ion-implanting the first conductive type impurities into the upward exposed channel region of the off-FET by removing the spacer;
removing the oxide layer and forming a gate electrode layer, upward exposing the first conductive type drain region and the second conductive type emitter region, on the substrate;
ion-implanting the second conductive type impurities into the second conductive type emitter region upward exposed by the gate electrode layer to form a second conductive type doping region; and
forming an upper metal layer, used as a cathode electrode, on the gate electrode layer, the first conductive type drain region, and the second conductive type doping region and a lower metal layer, used as an anode electrode, on a bottom surface of the substrate.

2. The method of claim 1 , wherein the forming of the channel region of the off-FET comprises performing an ion implantation process of ion-implanting the first conductive type impurities into the second conductive type emitter region upward exposed by the spacer and a photoresist pattern formed on the second conductive type emitter region upward exposed by the spacer by using the spacer and the photoresist pattern as an ion implantation mask.

3. The method of claim 1 , wherein the channel region of the off-FET is formed in a lateral direction between the junction surface of the second conductive type emitter region and the junction surface of the first conductive type drain region, under the spacer.

4. The method of claim 1 , wherein the ion-implanting of the first conductive type impurities into the channel region of the off-FET comprises:
removing the spacer by using an isotropic etching process; and
ion-implanting the first conductive type impurities into the channel region of the off-FET upward exposed by the isotropic etching process to adjust a turn-on voltage of the off-FET.

5. The method of claim 4 , wherein
the first conductive type impurities ion-implanted into the channel region of the off-FET are first conductive type impurities, and
an ion dose of the first conductive type impurities is about 1×10 11 cm −2 or about 1×10 13 cm −2 .

6. The method of claim 1 , wherein the ion-implanting of the first conductive type impurities into the channel region of the off-FET comprises:
further removing the spacer and the oxide layer by using an etching process;
forming another oxide layer on a surface of the substrate upward exposed by removing the spacer and the oxide layer;
forming another photoresist pattern on the other oxide layer and between the first conductive type base region and another first conductive type base region adjacent to the first conductive type base region; and
performing an ion implantation process of ion-implanting the first conductive type impurities into the channel region of the off-FET and a channel region of an on-FET adjacent to the channel region of the off-FET by using the other photoresist pattern as an ion implantation mask.

7. The method of claim 6 , wherein the channel region of the off-FET is a region under a surface of the first conductive type base region.

8. The method of claim 1 , wherein the ion-implanting of the first conductive type impurities into the channel region of the off-FET comprises:
further removing the oxide layer and the spacer by using an etching process;
forming another oxide layer on a whole surface of the substrate upward exposed by removing the oxide layer and the spacer; and
ion-implanting the first conductive type impurities into the channel region of the off-FET and a channel region of an on-FET adjacent to the channel region of the off-FET to form a threshold voltage adjustment layer on the whole surface of the substrate.

9. The method of claim 1 , wherein,
when the first conductive type impurities are p-type impurities, the second conductive type impurities are n-type impurities, and
when the first conductive type impurities are n-type impurities, the second conductive type impurities are p-type impurities.

Assignees

• Electronics & Telecommunications Res Inst

Inventors

• Park Kun Sik
• Won Jong Il
• Cho Doo Hyung
• Jang Hyun Gyu
• Jung Dong Yun

Classifications

• H10D18/655

  produced by insulated gate structures · CPC title

• H10D18/40

  with turn-on by field effect · CPC title

• H10D62/127

  of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs · CPC title

• H10D84/0105 Primary

  the built-in components being field-effect devices · CPC title

• H10D18/01 Primary

  Manufacture or treatment · CPC title