Semiconductor device and power conversion device
US-2024355888-A1 · Oct 24, 2024 · US
Method of manufacturing semiconductor device and semiconductor device
US9166017B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9166017-B2 |
| Application number | US-201414261497-A |
| Country | US |
| Kind code | B2 |
| Filing date | Apr 25, 2014 |
| Priority date | May 27, 2011 |
| Publication date | Oct 20, 2015 |
| Grant date | Oct 20, 2015 |
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- Title
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Abstract
Official abstract text for this publication.
Techniques capable of improving the yield of IGBTs capable of reducing steady loss, turn-off time, and turn-off loss are provided. Upon formation of openings in an interlayer insulting film formed on a main surface of a substrate, etching of a laminated insulating film of a PSG film and an SOG film and a silicon oxide film is once stopped at a silicon nitride film. Then, the silicon nitride film and the silicon oxide film are sequentially etched to form the openings. As a result, the openings are prevented from penetrating through an n-type source layer and a p + -type emitter layer having a thickness of 20 to 100 nm and reaching the substrate.
First claim
Opening claim text (preview).
What is claimed is: 1. A method of manufacturing a semiconductor device having an active portion and a peripheral portion outside the active portion and having elements of an IGBT formed in the active portion, the method comprising the steps of: (a) preparing a substrate exhibiting n-type conductivity type that is to serve as a base layer of the IGBT; (b) forming a first insulating film on a main surface of the substrate, the first insulating film including a plurality of thick-…
Assignees
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Classifications
- H10D64/112Primary
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9166017B2 cover?
- Techniques capable of improving the yield of IGBTs capable of reducing steady loss, turn-off time, and turn-off loss are provided. Upon formation of openings in an interlayer insulting film formed on a main surface of a substrate, etching of a laminated insulating film of a PSG film and an SOG film and a silicon oxide film is once stopped at a silicon nitride film. Then, the silicon nitride fil…
- Who is the assignee on this patent?
- Renesas Electronics Corp
- What technology area does this patent fall under?
- Primary CPC classification H10D64/112. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Oct 20 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).