Contact stacks to reduce hydrogen in semiconductor devices

Patent metadata

Field	Value
Publication number	US-11637185-B2
Application number	US-201816141301-A
Country	US
Kind code	B2
Filing date	Sep 25, 2018
Priority date	Sep 25, 2018
Publication date	Apr 25, 2023
Grant date	Apr 25, 2023

Abstract

Embodiments herein describe techniques for an integrated circuit that includes a substrate, a semiconductor device on the substrate, and a contact stack above the substrate and coupled to the semiconductor device. The contact stack includes a contact metal layer, and a semiconducting oxide layer adjacent to the contact metal layer. The semiconducting oxide layer includes a semiconducting oxide material, while the contact metal layer includes a metal with a sufficient Schottky-barrier height to induce an interfacial electric field between the semiconducting oxide layer and the contact metal layer to reject interstitial hydrogen from entering the semiconductor device through the contact stack. Other embodiments may be described and/or claimed.

First claim

What is claimed is:

1. An integrated circuit, comprising:
a substrate;
a semiconductor device on the substrate; and
a contact stack above the substrate and coupled to the semiconductor device, wherein the contact stack includes:
a contact metal layer;
a semiconducting oxide layer below the contact metal layer, wherein the semiconducting oxide layer includes a semiconducting oxide material; and
a semiconducting interlayer between the contact metal layer and the semiconducting oxide layer, wherein the contact metal layer covers an entirety of an uppermost surface of the semiconducting interlayer.

2. The integrated circuit of claim 1 , wherein the semiconducting oxide material is an n-type material or a p-type material.

3. The integrated circuit of claim 1 , wherein the semiconducting oxide material is an n-type material selected from the group consisting of ZnO, CdO, In 2 O 3 , Ga 2 O 3 , SnO 2 , IGZO, IZO, ITO, GZO, and TiO 2 , and the metal in the contact metal layer includes a material selected from the group consisting of Sn, W, Ir, Pt, Ru, Rh, and Ni.

4. The integrated circuit of claim 1 , wherein the semiconducting oxide material is a p-type material selected from the group consisting of SnO, Cu 2 O, CuO, VO 2 , NiO, ZnRh 2 O 4 , AlCuO 2 , SrCu 2 O 2 , and La 2 SeO 2 , and the metal in the contact metal layer includes Mn, Zn, or Cr.

5. The integrated circuit of claim 1 , wherein the semiconducting interlayer includes a material selected from the group consisting of InAs, InSb, InP, InN, CdSe, SnO2, and TiO2 when the semiconducting oxide material is an n-type material, or the semiconducting interlayer includes a material selected from the group consisting of Ge, Si, GaSb, AlSb, InSb, and CdTe when the semiconducting oxide material is a p-type material.

6. The integrated circuit of claim 1 , wherein the contact stack further includes:
a hydrogen bond breaking interlayer above the contact metal layer to break hydrogen bond to exploit electrostatics to reduce interstitial hydrogen entering the semiconductor device through the contact stack.

7. The integrated circuit of claim 6 , wherein the hydrogen bond breaking interlayer includes a material selected from the group consisting of Pt, Ni, and Rh.

8. The integrated circuit of claim 1 , wherein the semiconductor device is a transistor, and the contact stack is a source electrode of the transistor, or a drain electrode of the transistor.

9. The integrated circuit of claim 1 , wherein the contact stack is a contact plug or a via of the integrated circuit.

10. The integrated circuit of claim 1 , further comprising:
a contact plug adjacent to the contact stack.

11. The integrated circuit of claim 1 , wherein the contact metal layer includes a metal with a sufficient Schottky-barrier height (SBH) to induce an interfacial electric field between the semiconducting oxide layer and the contact metal layer to reject interstitial hydrogen from entering the semiconductor device through the contact stack.

12. The integrated circuit of claim 11 , wherein the interstitial hydrogen behaves as both a donor and an acceptor to the semiconducting oxide layer, and behaves exclusively as a donor to the semiconducting interlayer, the metal in the contact metal layer has a sufficient SBH to induce an interfacial electric field between the semiconducting interlayer and the contact metal layer to reject interstitial hydrogen from entering the semiconductor device through the contact stack.

13. The integrated circuit of claim 11 , wherein the interstitial hydrogen behaves exclusively as a donor in the semiconducting oxide layer, and the rejected interstitial hydrogen is positively charged atomic hydrogen.

14. The integrated circuit of claim 11 , wherein the interstitial hydrogen behaves exclusively as an acceptor in the semiconducting oxide layer, and the rejected interstitial hydrogen is negatively charged atomic hydrogen.

15. A computing device comprising:
a circuit board; and
an integrated circuit (IC) coupled to the circuit board, wherein the IC includes:
a contact stack above a substrate and coupled to a semiconductor device, wherein the contact stack includes:
a contact metal layer;
a semiconducting oxide layer below the contact metal layer, wherein the semiconducting oxide layer includes a semiconducting oxide material; and

a semiconducting interlayer between the contact metal layer and the semiconducting oxide layer, wherein the contact metal layer covers an entirety of an uppermost surface of the semiconducting interlayer.

16. The computing device of claim 15 , wherein the computing device is a device selected from the group consisting of a wearable device or a mobile computing device, the wearable device or the mobile computing device including one or more of an antenna, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, a Geiger counter, an accelerometer, a gyroscope, a speaker, and a camera coupled with the circuit board.

17. The computing device of claim 15 , wherein the contact metal layer includes a metal with a sufficient Schottky-barrier height (SBH) to induce an interfacial electric field between the semiconducting oxide layer and the contact metal layer to reject interstitial hydrogen from entering the semiconductor device through the contact stack.

18. The computing device of claim 17 , wherein the interstitial hydrogen behaves exclusively as a donor in the semiconducting oxide layer, and the rejected interstitial hydrogen is positively charged atomic hydrogen.

19. The computing device of claim 17 , wherein the interstitial hydrogen behaves exclusively as an acceptor in the semiconducting oxide layer, and the rejected interstitial hydrogen is negatively charged atomic hydrogen.

20. The computing device of claim 17 ,
wherein the interstitial hydrogen behaves as both a donor and an acceptor to the semiconducting oxide layer, and behaves exclusively as a donor to the semiconducting interlayer, the metal in the contact metal layer has a sufficient SBH to induce an interfacial electric field between the semiconducting interlayer and the contact metal layer to reject interstitial hydrogen from entering the semiconductor device through the contact stack.

Assignees

• Intel Corp

Inventors

• Weber Justin
• Kennel Harold
• Sharma Abhishek
• Jezewski Christopher
• Metz Matthew V
• Ghani Tahir
• Kavalieros Jack T
• Chu-Kung Benjamin
• Le Van H
• Sen Gupta Arnab

Classifications

• H10P36/00

  Gettering within semiconductor bodies · CPC title

• H10P14/3434

  being oxide semiconductor materials (Group IIB-VIA semiconductor materials H10P14/3424) · CPC title

• H10P14/3426

  Oxides · CPC title

• H10W20/01

  Manufacture or treatment · CPC title

• H10D64/64 Primary

  Electrodes comprising a Schottky barrier to a semiconductor · CPC title