Semiconductor device having capacitor and resistor and a method of forming the same

Patent metadata

Field	Value
Publication number	US-11637100-B2
Application number	US-202117400095-A
Country	US
Kind code	B2
Filing date	Aug 11, 2021
Priority date	Aug 11, 2021
Publication date	Apr 25, 2023
Grant date	Apr 25, 2023

Abstract

The present disclosure generally relates to a semiconductor device having a capacitor and a resistor and a method of forming the same. More particularly, the present disclosure relates to a metal-insulator-metal (MIM) capacitor and a thin film resistor (TFR) formed in a back end of line portion of an integrated circuit (IC) chip.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first inter-metal region above a substrate;
a second inter-metal region above the first inter-metal region;
a capacitor comprising:
a metal layer in the first inter-metal region;
a conductive layer in the second inter-metal region, the conductive layer is above the metal layer;
a first dielectric layer between the metal layer and the conductive layer;
a conductive film in the second inter-metal region, the conductive film has a first horizontal section above the conductive layer and a second horizontal section laterally adjacent to the conductive layer;
a second dielectric layer between the conductive layer and the conductive film;
a first interconnect via disposed upon the metal layer; and
a second interconnect via disposed upon the conductive layer.

2. The device of claim 1 , further comprising:
a third interconnect via disposed upon the second horizontal section of the conductive film.

3. The device of claim 2 , wherein the conductive layer includes a side surface, the conductive film includes a vertical section, and the vertical section of the conductive film overlaps with the side surface of the conductive layer.

4. The device of claim 3 , wherein the first horizontal section of the conductive film is integrally joined to the second horizontal section of the conductive film by the vertical section of the conductive film.

5. The device of claim 4 , wherein the conductive layer further includes an upper surface, and the first horizontal section of the conductive film overlaps with the upper surface of the conductive layer.

6. The device of claim 4 , wherein the first inter-metal region includes a dielectric material, and the second horizontal section of the conductive film is above the dielectric material in the first inter-metal region.

7. The device of claim 6 , wherein the first dielectric layer and second dielectric layer extend to lie below the second horizontal section of the conductive film.

8. The device of claim 6 , further comprising a resistor, the resistor comprising a resistive metallic film in the second inter-metal region, wherein the resistive metallic film of the resistor and the conductive film of the capacitor are a same material.

9. The device of claim 8 , wherein the resistive metallic film is above the dielectric material in the first inter-metal region.

10. The device of claim 9 , wherein the first dielectric layer and the second dielectric layer extend to lie below the resistive metallic film.

11. A semiconductor device comprising:
a first inter-metal region above a substrate;
a second inter-metal region above the first inter-metal region;
a capacitor comprising:
a metal layer in the first inter-metal region;
a conductive layer in the second inter-metal region, the conductive layer is above the metal layer;
a first dielectric layer between the metal layer and the conductive layer;
a conductive film in the second inter-metal region, the conductive film has a first horizontal section above the conductive layer and a second horizontal section laterally adjacent to the conductive layer;
a second dielectric layer between the conductive layer and the conductive film; and

a resistor comprising:
a resistive metallic film in the second inter-metal region, wherein the resistive metallic film of the resistor and the conductive film of the capacitor are a same material.

12. The device of claim 11 , further comprising
a first interconnect via disposed upon the metal layer;
a second interconnect via disposed upon the conductive layer; and
a third interconnect via disposed upon the second horizontal section of the conductive film.

13. The device of claim 12 , wherein the first inter-metal region includes a dielectric material, and the second horizontal section of the conductive film is above the dielectric material in the first inter-metal region.

14. The device of claim 12 , wherein the first dielectric layer is disposed upon the metal layer and the dielectric material in the first inter-metal region, the first dielectric layer extends to lie below the resistive metallic film and the second horizontal section of the conductive film.

15. The device of claim 14 , wherein the second dielectric layer is disposed upon the conductive layer and the first dielectric layer, the second dielectric layer extends to lie below the resistive metallic film and the second horizontal section of the conductive film.

16. A method of forming a resistor and a capacitor in a semiconductor device, the method comprising:
providing a first inter-metal region above a substrate, the first inter-metal region having a dielectric material;
forming a metal layer in the first inter-metal region;
forming a first dielectric layer on the metal layer;
forming a conductive layer on the first dielectric layer;
forming a second dielectric layer on the conductive layer;
forming a conductive film on the second dielectric layer, the conductive film has a first horizontal section above the conductive layer and a second horizontal section laterally adjacent to the conductive layer;
forming a resistive metallic film above the dielectric material in the first inter-metal region, wherein the resistive metallic film and the conductive film are made of a same material; and
forming a second inter-metal region above the first inter-metal region, wherein the conductive layer, the conductive film, and the resistive metallic film are in the second inter-metal region.

17. The method of claim 16 , further comprising
forming a first interconnect via on the metal layer;
forming a second interconnect via on the conductive layer; and
forming a third interconnect via on the second horizontal section of the conductive film.

18. The method of claim 17 , wherein the first dielectric layer is formed on the dielectric material in the first inter-metal region.

19. The method of claim 17 , wherein the conductive film and the resistive metallic film are formed simultaneously.

20. The method of claim 19 , wherein the second horizontal section of the conductive film is formed above the dielectric material in the first inter-metal region.

Assignees

• Globalfoundries Sg Pte Ltd

Inventors

• Wong Qiying
• Linewih Handoko
• Setiawan Yudi
• Feng Chengang
• Chwa Siow Lee

Classifications

• H10W20/498

  Resistive arrangements or effects of, or between, wiring layers · CPC title

• H10W20/496

  Capacitor integral with wiring layers · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10D86/85

  characterised by only passive components · CPC title

• H10D1/696 Primary

  comprising multiple layers, e.g. comprising a barrier layer and a metal layer (barrier layers to prevent diffusion of hydrogen or oxygen in perovskite based capacitors H10D1/688) · CPC title