Thin film resistor and top plate of capacitor sharing a layer

Patent metadata

Field	Value
Publication number	US-10840322-B2
Application number	US-201815940058-A
Country	US
Kind code	B2
Filing date	Mar 29, 2018
Priority date	Mar 29, 2018
Publication date	Nov 17, 2020
Grant date	Nov 17, 2020

Abstract

An integrated circuit (IC) includes a substrate with a semiconductor surface layer including functional circuitry having a plurality of interconnected transistors including a dielectric layer thereon with a metal stack including a plurality of metal levels over the dielectric layer. A thin film resistor (TFR) layer including at least one metal is within the metal stack. At least one capacitor is within the metal stack including a capacitor dielectric layer over a metal bottom plate formed from one of the metal levels. The capacitor top plate is formed from the TFR layer on the capacitor dielectric layer and there is at least one resistor lateral to the capacitor formed from the same TFR layer.

First claim

The invention claimed is:

1. A method of fabricating integrated circuits (ICs), comprising:
depositing a dielectric layer on a semiconductor surface layer on a substrate having a plurality of IC die formed in said semiconductor surface layer with each said IC die including functional circuitry comprising a plurality of interconnected transistors;
forming a metal layer of a metal level over said dielectric layer including for a bottom plate for a capacitor;
depositing at least one capacitor dielectric layer on said metal layer;
depositing a thin film resistor (TFR) layer comprising at least one metal on said capacitor dielectric layer;
forming a first pattern on said TFR layer;
etching said TFR layer using said first pattern including defining a top plate comprising said TFR layer on said capacitor dielectric layer and defining said TFR layer lateral to said capacitor form a resistor comprising said TFR layer, and
forming a second pattern on said capacitor dielectric layer, etching said capacitor dielectric layer, and then etching said metal layer to define said bottom plate and to complete said capacitor.

2. The method of claim 1 , wherein said etching said capacitor dielectric layer and etching said metal layer both utilize said pattern on said capacitor dielectric layer.

3. The method of claim 1 , wherein the metal level is metal level M1.

4. The method of claim 1 , wherein said metal for said TFR layer comprises chromium (Cr).

5. The method of claim 4 , wherein said TFR layer comprises silicon chromium (SiCr).

6. The method of claim 5 , wherein said SiCr layer further comprises carbon.

7. The method of claim 1 , wherein said TFR layer is 10 nm to 100 nm thick.

8. The method of claim 7 , wherein said TFR layer 25 nm to 35 nm thick.

9. The method of claim 1 , further comprising before said etching said TFR layer depositing a hardmask layer on said TFR layer.

10. The method of claim 9 , wherein said depositing said hardmask layer comprises utilizing tetraethoxysilane (TEOS) as a precursor material.

11. The method of claim 1 , wherein said capacitor dielectric layer is 200 A to 2,000 A thick and comprises at least two dielectric layers.

12. The method of claim 11 , wherein said at least two dielectric layers include a silicon nitride or a silicon oxynitride layer.

13. An integrated circuit (IC), comprising:
a substrate that includes a semiconductor surface layer including functional circuitry comprising a plurality of interconnected transistors including a dielectric layer thereon with a metal stack including a plurality of metal levels over said dielectric layer;
a thin film resistor (TFR) layer comprising at least one metal within said metal stack;
at least one capacitor within said metal stack including a capacitor dielectric layer over a metal bottom plate formed from one of said plurality of metal levels, and
a top plate for said capacitor comprising said TFR layer on said capacitor dielectric layer and at least one resistor lateral to said capacitor comprising said TFR layer; and
a hardmask layer over the TFR layer.

14. The IC of claim 13 , wherein said dielectric layer comprises a pre-metal dielectric (PMD) layer.

15. The IC of claim 13 , wherein the hardmask layer comprises silicon oxide.

16. The IC of claim 13 , wherein said metal for said TFR layer comprises chromium (Cr).

17. The IC of claim 16 , wherein said TFR layer comprises silicon chromium (SiCr).

18. The IC of claim 17 , wherein said SiCr layer further comprises carbon.

19. The IC of claim 13 , wherein a thickness of said TFR layer is 10 nm to 100 nm.

20. The IC of claim 19 , wherein said thickness of said TFR layer is 25 nm to 35 nm.

21. The IC of claim 13 , wherein said capacitor dielectric layer is 200 A to 2,000 A thick and comprises at least two dielectric layers.

22. The IC of claim 21 , wherein said at least two dielectric layers include a silicon nitride or a silicon oxynitride layer.

Assignees

• Texas Instruments Inc

Inventors

• Kande Dhishan
• Shao Ye
• Curran David

Classifications

• H10P76/4085

  characterised by the processes involved to create the masks · CPC title

• H10P76/405

  characterised by their composition, e.g. multilayer masks · CPC title

• H10P50/283

  by chemical means · CPC title

• H10P50/264

  by chemical means · CPC title

• H10P50/71

  using masks for conductive or resistive materials · CPC title