Clustered parity for NAND data placement schema

Patent metadata

Field	Value
Publication number	US-11635894-B2
Application number	US-201916488696-A
Country	US
Kind code	B2
Filing date	Mar 15, 2019
Priority date	Mar 16, 2018
Publication date	Apr 25, 2023
Grant date	Apr 25, 2023

Abstract

Disclosed in some examples are improvements to data placement architectures in NAND that provide additional data protection through an improved NAND data placement schema that allows for recovery from certain failure scenarios. The present disclosure stripes data diagonally across page lines and planes to enhance the data protection. Parity bits are stored in SLC blocks for extra protection until the block is finished writing and then the parity bits may be deleted.

First claim

The invention claimed is:

1. A NAND memory device comprising:
an array of NAND memory cells organized into multiple planes and addressable by multiple page lines; and
a controller configured to perform operations comprising:
programming a received data item into a first data stripe by programming a first portion of the received data item into a first page line of the multiple page lines on a first plane of the multiple planes, a second portion of the received data item into a second page line of the multiple page lines on a second plane of the multiple planes, and a third portion of the received data item into a third page line of the multiple page lines on a third plane of the multiple planes, wherein a third page number of the third page line is greater than a second page number of the second page line and a third plane number of the third plane is greater than a second plane number of the second plane, and wherein a second page number of the second page line is greater than a first page number of the first page line and a second plane number of the second plane is greater than a first plane number of a first plane;
calculating a parity value for the received data item using the first portion, second portion, and third portion;
storing the parity value with multiple other parity values in a first parity cluster of multiple parity clusters, each particular one of the other parity values storing a parity value for a different stripe, the parity values stored in the multiple page lines and the multiple planes;
compressing the parity value and the multiple other parity values by combining parity values occupying a same plane number and a same page number relative to the first page number of a parity cluster within the multiple parity clusters to create compressed parity values;
storing the compressed parity values in the array of NAND cells and
wherein the operations of storing the compressed parity values in the array of NAND cells comprises overwriting the multiple other parity values with the compressed parity values.

2. The NAND memory device of claim 1 , wherein the operations comprise:
receiving an indication that a first portion of the received data item read from the array of NAND memory cells failed an Error Correction Code check; and
recovering the first portion using a compressed parity value corresponding to the received data item, the second and third portions of the received data item, and other portions of other data items corresponding to the compressed parity value.

3. The NAND memory device of claim 1 , wherein the operations of compressing the parity value and the multiple other parity values by combining parity values occupying a same plane number and a same page number relative to the first page number of the parity cluster within the multiple parity clusters to create compressed parity values comprises utilizing an XOR operation.

4. The NAND memory device of claim 1 , wherein the operations of calculating the parity value for the received data item using the first portion, second portion, and third portion comprises applying an XOR operator to the first portion, second portion, and third portion.

5. The NAND memory device of claim 1 , wherein the first portion is a lower page, the second portion is an upper page, and the third portion is an extra page.

6. The NAND memory device of claim 5 , wherein a second received data item is programmed into a second stripe and wherein the first portion of the second received data item is an upper page, the second portion of the second received data item is the extra page and the third portion of the second received data item is the extra page.

7. The NAND memory device of claim 1 , wherein the operations of compressing the parity value and multiple other parity values is responsive to completion of NAND block programming.

8. A non-transitory machine-readable medium, comprising instructions, which when executed by a machine, cause the machine to perform operations comprising:
programming a received data item into a first data stripe by programming a first portion of the received data item into a first page line of multiple page lines on a first plane of multiple planes of a NAND array, a second portion of the received data item into a second page line of the multiple page lines on a second plane of the multiple planes, and a third portion of the received data item into a third page line of the multiple page lines on a third plane of the multiple planes, wherein a third page number of the third page line is greater than a second page number of the second page line and a third plane number of the third plane is greater than a second plane number of the second plane, and wherein a second page number of the second page line is greater than a first page number of the first page line and a second plane number of the second plane is greater than a first plane number of a first plane;
calculating a parity value for the received data item using the first portion, second portion, and third portion;
storing the parity value with multiple other parity values in a first parity cluster of multiple parity clusters, each particular one of the other parity values storing a parity value for a different stripe, the parity values stored in the multiple page lines and the multiple planes;
compressing the parity value and the multiple other parity values by combining parity values occupying a same plane number and a same page number relative to the first page number of a parity cluster within the multiple parity clusters to create compressed parity values;
storing the compressed parity values in the NAND array; and

wherein the operations of storing the compressed parity values in the array of NAND cells comprises overwriting the multiple other parity values with the compressed parity values.

9. The non-transitory machine-readable medium of claim 8 , wherein the operations further comprise:
receiving an indication that a first portion of the received data item read from the NAND array of NAND memory cells failed an Error Correction Code check; and
recovering the first portion using a compressed parity value corresponding to the received data item, the second and third portions of the received data item, and other portions of other data items corresponding to the compressed parity value.

10. The non-transitory machine-readable medium of claim 8 , wherein the operations of compressing the parity value and the multiple other parity values by combining parity values occupying a same plane number and a same page number relative to the first page number of the parity cluster within the multiple parity clusters to create compressed parity values comprises utilizing an XOR operation.

11. The non-transitory machine-readable medium of claim 8 , wherein the operations of calculating the parity value for the received data item using the first portion, second portion, and third portion comprises applying an XOR operator to the first portion, second portion, and third portion.

12. The non-transitory machine-readable medium of claim 8 , wherein the first portion is a lower page, the second portion is an upper page, and the third portion is an extra page.

13. The non-transitory machine-readable medium of claim 12 , wherein a second received data item is programmed into a second stripe and wherein the first portion of the second received data item is an upper page, the second portion of the second received data item is the extra page and the third portion of the third received data item is the extra page.

14. The non-transitory machine-readable medium of claim 8 , wherein the operations of compressing the parit

Assignees

• Micron Technology Inc

Inventors

• Papa Paolo
• Manganelli Carminantonio
• Iaculo Massimo
• D'Eliseo Giuseppe
• Sassara Alberto

Classifications

• G06F3/0655

  Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices · CPC title

• G06F3/0608 Primary

  Saving storage space on storage systems · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F11/1068 Primary

  in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence) · CPC title