Display driver, display device and method of driving display panel

Patent metadata

Field	Value
Publication number	US-11635845-B2
Application number	US-202017036751-A
Country	US
Kind code	B2
Filing date	Sep 29, 2020
Priority date	Sep 22, 2017
Publication date	Apr 25, 2023
Grant date	Apr 25, 2023

Abstract

A display driver comprises a touch controller configured to perform touch sensing on a display panel during a vertical sync period. A first field of the vertical sync period comprises a display period and a touch sensing period following the display period. A start timing of the touch sensing period is controlled by an internal clock signal. A first counter is configured to, responsive to completion of the touch sensing, start a counting operation in synchronization with the internal clock signal. Gate control signal generator circuitry is configured to control a gate driver that is configured to drive a plurality of gate lines of the display panel. A gate line that is to be driven first to a high level during a second field following the first field is driven to the high level responsive to a count value of the first counter during the first field.

First claim

What is claimed is:

1. A display driver, comprising:
a controller configured to perform touch sensing during a first touch sensing period of a first field of a vertical sync period and to perform touch sensing during a second touch sensing period of a second field of the vertical sync period; and
gate control signal generator circuitry configured to:
generate a first set of multi-phase clock signals configured to control first gate line drive signals supplied to gate lines of a display panel during a first display period of the first field of the vertical sync period; and
generate a second set of multi-phase clock signals configured to control second gate line drive signals supplied to the gate lines of the display panel during a second display period of the second field of the vertical sync period, wherein a start time of a first multi-phase clock signal of the second set of multi-phase clock signals is based on an internal clock signal of the display driver and is before a start time of the second field of the vertical sync period.

2. The display driver of claim 1 , wherein the first field starts after an assertion of a vertical sync signal, wherein a length of a delay between the assertion of the vertical sync signal and the start of the first field corresponds to one or more assertions of a horizontal sync signal.

3. The display driver of claim 2 , wherein a length of the first touch sensing period corresponds to a frequency of the internal clock signal of the display driver and a frequency of the horizontal sync signal.

4. The display driver of claim 1 , further comprising:
timer circuitry including a counter configured to count a second clock signal, wherein the first multi-phase clock signal of the second set of multi-phase clock signals is generated in response to a count value of the counter reaching a first value.

5. The display driver of claim 4 , wherein the counter is configured to count the second clock signal in response to completion of the first touch sensing period.

6. The display driver of claim 1 , wherein each of the first gate line drive signals is driven high in response to an assertion of a respective one of the first multi-phase clock signals.

7. A display device, comprising:
a display panel comprising gate lines; and
a display driver coupled to the display panel and configured to:
perform touch sensing during a first touch sensing period of a first field of a vertical sync period and perform touch sensing during a second touch sensing period of a second field of the vertical sync period;
generate a first set of multi-phase clock signals configured to control first gate line drive signals supplied to the gate lines of the display panel during a first display period of the first field; and
generate a second set of multi-phase clock signals configured to control second gate line drive signals supplied to the gate lines of the display panel during a second display period of the second field of the vertical sync period, wherein a start time of a first multi-phase clock signal of the second set of multi-phase clock signals is based on an internal clock signal of the display driver and is before a start time of the second field of the vertical sync period.

8. The display device of claim 7 , wherein the first field starts after an assertion of a vertical sync signal, wherein a length of a delay between the assertion of the vertical sync signal and the start of the first field corresponds to one or more assertions of a horizontal sync signal.

9. The display device of claim 8 , wherein a length of the first touch sensing period corresponds to a frequency of the internal clock signal of the display driver and a frequency of the horizontal sync signal.

10. The display device of claim 8 , wherein the display driver is further configured to count a second clock signal, and wherein the first multi-phase clock signal of the second set of multi-phase clock signals is generated in response to the count reaching a first value.

11. The display device of claim 10 , wherein the display driver is configured to count the second clock signal in response to completion of the first touch sensing period.

12. The display device of claim 7 , wherein each of the first gate line drive signals is driven high in response to an assertion of a respective one of the first multi-phase clock signals.

13. A method for driving a display device having a display driver, the method comprising:
performing touch sensing during a first touch sensing period of a first field of a vertical sync period;
generating first multi-phase clock signals configured to control first gate line drive signals supplied to gate lines of a display panel during a first display period of the first field, wherein the first field starts after a delay from an assertion of the vertical sync period, and wherein a start timing of the first display period and a start timing of the first touch sensing period are synchronous with an internal clock signal of the display driver;
performing touch sensing during a second touch sensing period of a second field of the vertical sync period; and
generating a second set of multi-phase clock signals configured to control second gate line drive signals supplied to the gate lines of the display panel during a second display period of the second field of the vertical sync period, wherein a start time of a first multi-phase clock signal of the second set of multi-phase clock signals is based on the internal clock signal of the display driver and is before a start time of the second field of the vertical sync period.

14. The method of claim 13 , wherein the first field starts after an assertion of a vertical sync signal, wherein a length of a delay between the assertion of the vertical sync signal and the start of the first field corresponds to one or more assertions of a horizontal sync signal.

15. The method of claim 14 , wherein a length of the first touch sensing period corresponds to a frequency of the internal clock signal of the display driver and a frequency of the horizontal sync signal.

16. The method of claim 13 , further comprising:
counting a second clock signal, wherein the first multi-phase clock signal of the second set of multi-phase clock signals is generated in response to a count value reaching a first value.

17. The method of claim 16 , further comprising:
counting the second clock signal in response to completion of the first touch sensing period.

18. The display driver according to claim 1 , wherein the gate control signal generator circuitry is configured to prevent a time period between an end time of the first set of multi-phase clock signals and a start time of the second set of multi-phase clock signals from exceeding a predetermined amount of time.

19. The display device according to claim 7 , wherein the display driver is configured to prevent a time period between an end time of the first set of multi-phase clock signals and a start time of the second set of multi-phase clock signals from exceeding a predetermined amount of time.

20. The method according to claim 13 , wherein the display driver prevents a time period between an end time of the first set of multi-phase clock signals and a start time of the second set of multi-phase clock signals from exceeding a predetermined amount of time.

Assignees

• Synaptics Japan Gk

Inventors

• Takeuchi Makoto
• Ota Shigeru
• Shikata Atsushi
• Suzuki Kentaro
• Shimbo Jiro

Classifications

• G06F3/04166 Primary

  Details of scanning methods, e.g. sampling time, grouping of sub areas or time sharing with display driving (Synchronisation with the driving of the display or the backlighting unit to avoid interferences generated internally G06F3/04184) · CPC title

• G06F3/0412

  Digitisers structurally integrated in a display · CPC title

• G06F3/04184

  Synchronisation with the driving of the display or the backlighting unit to avoid interferences generated internally · CPC title

• G06F3/044

  by capacitive means · CPC title

• G09G2310/067

  Special waveforms for scanning, where no circuit details of the gate driver are given · CPC title