Techniques for control of quantum systems and related systems and methods

Patent metadata

Field	Value
Publication number	US-11635456-B2
Application number	US-201716076411-A
Country	US
Kind code	B2
Filing date	Feb 10, 2017
Priority date	Feb 12, 2016
Publication date	Apr 25, 2023
Grant date	Apr 25, 2023

Abstract

The present application describes a waveform processor for control of quantum mechanical systems. The waveform processor may be used to control quantum systems used in quantum computation, such as qubits. According to some embodiments, a waveform processor includes a first sequencer configured to sequentially execute master instructions according to a defined order and output digital values in response to the executed master instructions, and a second sequencer coupled to the first sequencer and configured to generate analog waveforms at least in part by transforming digital waveforms according to digital values received from the first sequencer. The analog waveforms are applied to a quantum system. In some embodiments, the waveform processor further includes a waveform analyzer configured to integrate analog waveforms received from a quantum system and output results of said integration to the first sequencer.

First claim

What is claimed is:

1. A waveform processor comprising:
one or more data storage devices that include:
a first memory for storing a plurality of master instructions, wherein a master instruction comprises a plurality of digital data fields and the master instructions have a defined order; and
a second memory for storing a plurality of digital waveforms;

a first sequencer comprising a first plurality of logic blocks configured to access the first memory and sequentially execute the master instructions according to their defined order, the first sequencer having a first digital output configured to output digital values based at least in part on results of executing the master instructions;
a second sequencer coupled to the first sequencer and configured to receive values from the first digital output, the second sequencer comprising a second plurality of logic blocks configured to:
access the second memory;
generate analog waveforms at least in part by transforming one of the plurality of digital waveforms according to one or more of the digital values received from the first sequencer; and
output the generated analog waveforms to an external system; and

a waveform analyzer comprising a third plurality of logic blocks configured to integrate analog waveforms received from the external system and to output results of said integration to the first sequencer,
wherein transforming one of the plurality of digital waveforms by the second sequencer comprises performing a linear transformation of the one of the plurality of digital waveforms based at least in part on the one or more digital values received from the first sequencer.

2. The waveform processor of claim 1 ,
wherein the one or more data storage devices further include a third memory for storing a plurality of waveform instructions, wherein a waveform instruction comprises a plurality of digital data fields and the waveform instructions have a defined order, and
wherein the second plurality of logic blocks of the second sequencer are further configured to:
access the third memory and sequentially execute the waveform instructions according to their defined order; and
generate said analog waveforms according to the executed waveform instructions.

3. The waveform processor of claim 2 , wherein the waveform instructions include at least a first branch instruction and wherein the second sequencer is further configured to identify a non-sequential waveform instruction of the plurality of waveform instructions to execute subsequent to the first branch instruction based at least in part on a digital signal received by the second sequencer from the first sequencer.

4. The waveform processor of claim 2 , wherein the second plurality of logic blocks of the second sequencer are further configured to repeatedly execute the plurality of waveform instructions according to their defined order.

5. The waveform processor of claim 1 , wherein the master instructions include at least a first branch instruction and wherein the first sequencer is further configured to identify a non-sequential master instruction of the plurality of master instructions to execute subsequent to the first branch instruction based at least in part on a digital signal received by the first sequencer.

6. The waveform processor of claim 5 , wherein the digital signal received by the first sequencer is received by the first sequencer from the waveform analyzer and comprises a result of said integration by the waveform analyzer.

7. The waveform processor of claim 5 , wherein the first sequencer is further configured to output a digital instruction to the second sequencer based at least in part on the result of said integration received by the first sequencer from the waveform analyzer.

8. The waveform processor of claim 1 , wherein the integration of analog waveforms by the waveform analyzer is triggered by execution of a master instruction by the first sequencer.

9. The waveform processor of claim 1 , wherein the external system is a quantum system including a qubit, and wherein the generated analog waveforms are designed to rotate a state of the qubit.

10. The waveform processor of claim 1 , wherein the first sequencer is further configured with a second digital output configured to output digital values based at least in part on results of executing the master instructions, the waveform processor further comprising:
a third sequencer coupled to the first sequencer and configured to receive values from the second digital output, the third sequencer configured to output digital values according to one or more of the digital values received from the first sequencer.

11. The waveform processor of claim 1 , wherein the one or more data storage devices, the first sequencer, the second sequencer and the waveform analyzer are assembled on a single substrate.

12. The waveform processor of claim 1 , wherein the first sequencer, the second sequencer and the waveform analyzer are embodied in a field-programmable gate array.

13. The waveform processor of claim 1 , wherein the first sequencer, the second sequencer and the waveform analyzer are embodied in an application specific integrated circuit.

14. The waveform processor of claim 1 , wherein the first sequencer, the second sequencer and the waveform analyzer are configured to receive a common clock signal.

15. The waveform processor of claim 1 , wherein the second sequencer is configured to generate the analog waveforms as comprising IQ waveform pairs.

16. The waveform processor of claim 1 , wherein the second sequencer is configured to generate the analog waveforms as single-sideband modulated waveforms.

17. The waveform processor of claim 1 , wherein:
the second sequencer comprises a digital-to-analog converter; and
the waveform analyzer comprises an analog-to-digital converter.

18. A system comprising the waveform processor of claim 1 and a superconducting qubit coupled to the waveform processor.

19. A system comprising a plurality of instances of the waveform processor of claim 1 communicatively coupled to one another.

20. A method comprising:
selecting, by a first sequencer that comprises a first plurality of logic blocks, a first master sequence instruction from a plurality of master sequence instructions stored in a first memory of one or more data storage devices, wherein a master sequence instruction comprises a plurality of digital data fields and the master instructions have a defined order;
executing, by the first sequencer, the first master sequence instruction;
outputting, by the first sequencer, one or more digital values to a second sequencer comprising a digital-to-analog converter and a second plurality of logic blocks;
generating, by the second sequencer, a first analog waveform at least in part by performing a linear transformation of one of a plurality of digital waveforms based at least in part on the one or more digital values received from the first sequencer;
applying the first analog waveform to a system;
integrating, by a waveform analyzer comprising a first analog-to-digital converter and a third plurality of logic blocks assembled on a substrate, a first received analog waveform from the system;
providing, by the waveform analyzer, a result of the integration to the first sequencer; and
executing, by the first sequencer, a second master sequence instruction of the plurality of master sequence instructions based on the received result from the waveform analyzer.

21. The method of claim 20

Assignees

• Univ Yale

Inventors

• Ofek Nissim
• Frunzio Luigi
• Devoret Michel
• Schoelkopf Iii Robert J

Classifications

• G06N10/40

  Physical realisations or architectures of quantum processors or components for manipulating qubits, e.g. qubit coupling or qubit control · CPC title

• G06N10/70

  Quantum error correction, detection or prevention, e.g. surface codes or magic state distillation · CPC title

• G01R33/1284

  Spin resolved measurements; Influencing spins during measurements, e.g. in spintronics devices · CPC title

• G01R23/16 Primary

  Spectrum analysis; Fourier analysis · CPC title

• G06F17/14

  Fourier, Walsh or analogous domain transformations {, e.g. Laplace, Hilbert, Karhunen-Loeve, transforms (for correlation function computation G06F17/156; spectrum analysers G01R23/16)} · CPC title