Arithmetic logic unit design in column analog to digital converter with shared gray code generator for correlated multiple samplings

Patent metadata

Field	Value
Publication number	US-11632512-B2
Application number	US-202117180520-A
Country	US
Kind code	B2
Filing date	Feb 19, 2021
Priority date	Feb 19, 2021
Publication date	Apr 18, 2023
Grant date	Apr 18, 2023

Abstract

An arithmetic logic unit (ALU) includes a front end latch stage coupled to latch Gray code (GC) outputs of a GC generator in response to a comparator output. A signal latch stage is coupled to latch outputs of the front end latch stage. A GC to binary stage is coupled to generate a binary representation of the GC outputs latched in the signal latch stage. First inputs of an adder stage are coupled to receive outputs of the GC to binary stage. Outputs of the adder stage are generated in response to the first inputs and second inputs of the adder stage. A pre-latch stage is coupled to latch outputs of the adder stage. A feedback latch stage is coupled to latch outputs of the pre-latch stage. The second inputs of the adder stage are coupled to receive outputs of the feedback latch stage.

First claim

What is claimed is:

1. An arithmetic logic unit (ALU), comprising:
a front end latch stage coupled to a Gray code (GC) generator to latch GC outputs of the GC generator in response to a comparator output;
a signal latch stage coupled to latch outputs of the front end latch stage in response to a signal latch enable signal;
a GC to binary stage coupled to generate a binary representation of the GC outputs latched in the signal latch stage;
an adder stage including first inputs and second inputs, wherein the first inputs of the adder stage are coupled to receive outputs of the GC to binary stage, wherein outputs of the adder stage are generated in response to the first inputs and the second inputs of the adder stage;
a pre-latch stage coupled to latch outputs of the adder stage in response to a pre-latch enable signal; and
a feedback latch stage coupled to latch outputs of the pre-latch stage in response to a feedback latch enable signal, wherein the second inputs of the adder stage are coupled to receive outputs of the feedback latch stage.

2. The ALU of claim 1 , wherein the outputs of the feedback latch stage include first outputs and second outputs, wherein the first outputs of the feedback latch stage are the latched outputs of the pre-latch stage, wherein the second outputs of the feedback latch stage are inverted latched outputs of the pre-latch stage, wherein the ALU further comprises:
a multiplexer stage coupled between the feedback latch stage and the adder stage, wherein the multiplexer is configured to couple either the first outputs or the second outputs of the feedback latch stage to the second inputs of the adder stage in response to an adder operation signal.

3. The ALU of claim 2 , wherein a least significant bit (LSB) of the adder stage is coupled to receive a low value at a carry-in input when the multiplexer stage is configured to couple the first outputs of the feedback latch stage to the second inputs of the adder stage,
wherein the LSB of the adder stage is further coupled to receive a high value at the carry-in input when the multiplexer stage is configured to couple the second outputs of the feedback latch stage to the second inputs of the adder stage.

4. The ALU of claim 3 , wherein the adder stage is configured to add a feedback value latched in the feedback latch stage and the binary representation of the GC outputs latched in the signal latch stage when the multiplexer stage is configured to couple the first outputs of the feedback latch stage to the second inputs of the adder stage.

5. The ALU of claim 3 , wherein the adder stage is configured to add a two's complement representation of a feedback value latched in the feedback latch stage and the binary representation of the GC outputs latched in the signal latch stage when the multiplexer stage is configured to couple the second outputs of the feedback latch stage to the second inputs of the adder stage.

6. The ALU of claim 1 , wherein the GC outputs of the GC generator include N bits, wherein the GC to binary stage includes N exclusive-OR (XOR) gates,
wherein first inputs of the N XOR gates are coupled to receive respective bits of the GC outputs of the GC generator,
wherein second inputs of N−1 XOR gates corresponding to least N−1 significant bits of the GC outputs of the GC generator are coupled to receive respective outputs of nearest neighboring XOR gates corresponding to a higher bit value,
wherein a second input of an Nth XOR gate corresponding to a most significant bit (MSB) of the GC outputs of the GC generator is coupled to receive a low value when the outputs of the N XOR gates of the GC to binary stage are configured to generate the binary representations of the GC outputs.

7. The ALU of claim 6 , wherein the second input of the Nth XOR gate corresponding to the MSB of the GC outputs of the GC generator is coupled to receive a high value when the outputs of the N XOR gates of the GC to binary stage are configured to generate inverted binary representations of the GC outputs.

8. The ALU of claim 7 , wherein a least significant bit (LSB) of the adder stage is coupled to receive a low value at a carry-in input when the second input of the Nth XOR gate corresponding to the MSB of the GC outputs of the GC generator is coupled to receive the low value,
wherein the LSB of the adder stage is coupled to receive a high value at the carry-in input when the second input of the Nth XOR gate corresponding to the MSB of the GC outputs of the GC generator is coupled to receive the high value.

9. The ALU of claim 8 , wherein the adder stage is configured to add the binary representation of the GC outputs latched in the signal latch stage and a feedback value latched in the feedback latch stage when the outputs of the N XOR gates of the GC to binary stage are configured to generate the binary representations of the GC outputs.

10. The ALU of claim 8 , wherein the adder stage is configured to add a two's complement representation of the GC outputs latched in the signal latch stage and a feedback value latched in the feedback latch stage when the outputs of the N XOR gates of the GC to binary stage are configured to generate the inverted binary representations of the GC outputs.

11. The ALU of claim 1 , further comprising a pulse generator coupled to generate a front end latch enable signal in response to the comparator output, wherein the front end latch stage is coupled to latch the GC outputs of the GC generator in response to the front end latch enable signal.

12. The ALU of claim 11 , further comprising a bypass switch coupled between an input of the pulse generator and an output of the pulse generator, wherein the front end latch enable signal is substantially equal to the comparator output when the bypass switch is closed, wherein the front end latch enable signal is substantially equal to an output of the pulse generator when the bypass switch is opened.

13. The ALU of claim 1 , wherein the feedback latch stage is configured to be reset in response to a feedback latch reset signal.

14. The ALU of claim 1 , further comprising a data latch stage coupled to latch outputs of the pre-latch stage in response to a data latch enable signal.

15. The ALU of claim 1 , wherein the ALU is one of a plurality of ALUs coupled to a pixel array of an imaging system, wherein the plurality of ALUs are configured to determine a difference between an accumulated sum of one or more signal level samples and an accumulated sum of one or more black level samples from each of a plurality of pixel circuits of the pixel array.

16. An imaging system, comprising:
a pixel array including a plurality of pixel circuits arranged into rows and columns, wherein each one of the plurality of pixel circuits is coupled to generate an analog image data signal in response to incident light;
control circuitry coupled to the pixel array to control operation of the pixel array; and
a readout circuit coupled to the pixel array through a plurality of column bit lines, wherein the readout circuit comprises:
a plurality of comparators, wherein each one of the plurality of comparators is coupled to receive a ramp signal, wherein each one of the plurality of comparators is further coupled to a respective one of a plurality of column bit lines to receive a respective analog image data signal, wherein each one of the plurality of comparators is coupled to generate a respective comparator output in response to a comparison of the respective analog image data signal and the ramp signal;
a Gray code (GC) generator coupled to generate GC outputs; and
a plurality of a

Assignees

• Omnivision Tech Inc

Inventors

• Fan Lihang
• Qu Min
• Tsai Chao-Fang
• Chang Chun-Hsiang

Classifications

• G06F7/575 Primary

  Basic arithmetic logic units, i.e. devices selectable to perform either addition, subtraction or one of several logical operations, using, at least partially, the same circuitry · CPC title

• H04N25/78

  Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters · CPC title

• H04N25/618

  for random or high-frequency noise · CPC title

• H04N25/616

  involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling · CPC title

• H04N25/46

  by combining or binning pixels · CPC title