High quiescent current control

Patent metadata

Field	Value
Publication number	US-11626841-B2
Application number	US-202017136427-A
Country	US
Kind code	B2
Filing date	Dec 29, 2020
Priority date	Jul 10, 2020
Publication date	Apr 11, 2023
Grant date	Apr 11, 2023

Abstract

A circuit is provided. In some examples, the circuit includes a first transistor having a gate and a drain coupled together and a current source coupled to the drain of the first transistor. A second transistor has a drain coupled to a source of the first transistor. A third transistor has a gate coupled to the gate of the first transistor. A fourth transistor has a drain coupled to a source of the third transistor and a gate of the fourth transistor is coupled to a gate of the second transistor. In some examples, the third transistor is configured to limit a first current between the third transistor and the fourth transistor based on an output voltage.

First claim

What is claimed is:

1. A circuit comprising:
a first transistor having a gate and a drain coupled together;
a current source coupled to the drain of the first transistor;
a second transistor having a drain coupled to a source of the first transistor and to an output voltage node;
a third transistor having a gate coupled to the gate of the first transistor; and
a fourth transistor having a drain coupled to a source of the third transistor and a gate of the fourth transistor is coupled to a gate of the second transistor.

2. The circuit of claim 1 , wherein:
the first, second, third, and fourth transistors comprise N-MOS transistors.

3. The circuit of claim 1 , wherein:
the first, second, third, and fourth transistors comprise P-MOS transistors.

4. The circuit of claim 2 , further wherein:
the current source is coupled to a voltage source.

5. The circuit of claim 3 , wherein:
the current source is coupled to a ground.

6. The circuit of claim 1 , further comprising:
a fifth transistor having a drain coupled to the drain of the second transistor.

7. The circuit of claim 6 , further comprising:
a current selector coupled to the fifth transistor and the third transistor, wherein the current selector includes three transistors.

8. The circuit of claim 7 , further comprising:
a sixth transistor having a drain coupled to the current selector.

9. An electronic device comprising:
a current source;
a first transistor coupled to the current source and an output voltage;
a second transistor coupled to the first transistor;
a third transistor coupled to the first transistor, wherein the first transistor is configured to bias the third transistor based on the output voltage and the current source; and
a fourth transistor coupled to the second transistor and the fourth transistor coupled in series with the third transistor, wherein the third transistor is configured to limit a first current between the third transistor and the fourth transistor based on the output voltage.

10. The electronic device of claim 9 , wherein:
the first, second, third, and fourth transistors comprise N-MOS transistors.

11. The electronic device of claim 9 , wherein:
the first, second, third, and fourth transistors comprise P-MOS transistors.

12. The electronic device of claim 9 , further comprising:
a fifth transistor;
a current selector coupled with the third transistor and the fifth transistor, wherein the current selector is configured to output a lesser of a second current associated with the second transistor and a third current associated with the fifth transistor; and
a sixth transistor coupled to the output of the current selector.

13. The electronic device of claim 9 , wherein:
the first transistor comprises a diode configuration, wherein a gate of the first transistor is coupled to a drain of the first transistor.

14. The electronic device of claim 12 , wherein:
the current selector includes:
a seventh transistor coupled to the third transistor, wherein a gate of the seventh transistor is coupled to a drain of the seventh transistor;
an eighth transistor, wherein a gate of the eighth transistor is coupled to the gate of the seventh transistor; and
a ninth transistor coupled to the eighth transistor.

15. An amplifier, comprising:
an input stage configured to receive an input voltage signal and to provide a drive signal;
an amplifier stage configured to receive the drive signal and to provide an amplified signal in response to a bias signal and the drive signal;
an output stage configured to receive the amplified signal and provide an output voltage; and
a control circuit coupled to the amplifier stage and the output stage, the control circuit configured to provide the bias signal to the amplifier stage, wherein the control circuit includes:
a current source;
a voltage sensor coupled to the current source, the voltage sensor configured to sense the output voltage; and
a current limiter coupled to the voltage sensor, the current limiter configured to limit a first current based on the output voltage.

16. The amplifier of claim 15 , wherein the control circuit includes:
a current selector coupled to the current limiter, wherein the current selector is configured to sense a second current associated with a first transistor of the output stage.

17. The amplifier of claim 16 , wherein the control circuit includes:
a current sensor configured to sense a third current associated with a second transistor of the output stage.

18. The amplifier of claim 17 , wherein:
the current selector is configured to output a lesser current of the second current and the third current; and
the bias signal is based on the lesser current that is output from the current selector.

19. The amplifier of claim 15 , wherein:
the voltage sensor includes a transistor in a diode configuration, wherein a gate of the transistor is coupled to a drain of the transistor.

20. The amplifier of claim 17 , wherein:
the voltage sensor is configured to bias the current limiter to increase limitation of the first current based on a corresponding increase in the output voltage, and
the first current between the current selector and the current sensor.

Assignees

• Texas Instruments Inc

Inventors

• Agarwal Nitin
• Roy Aniruddha

Classifications

• H03F2200/504

  the supply voltage or current being continuously controlled by a controlling signal, e.g. the controlling signal of a transistor implemented as variable resistor in a supply path for, an IC-block showed amplifier · CPC title

• H03F1/0233 Primary

  by using a signal derived from the output signal, e.g. bootstrapping the voltage supply · CPC title

• H03F1/3205

  in field-effect transistor amplifiers · CPC title

• H03F3/3028

  with symmetrical driving of the end stage · CPC title