Antenna gate field plate on 2DEG planar FET

Patent metadata

Field	Value
Publication number	US-11626513-B2
Application number	US-201816218886-A
Country	US
Kind code	B2
Filing date	Dec 13, 2018
Priority date	Dec 13, 2018
Publication date	Apr 11, 2023
Grant date	Apr 11, 2023

Abstract

Embodiments include a transistor and methods of forming a transistor. In an embodiment, the transistor comprises a semiconductor channel, a source electrode on a first side of the semiconductor channel, a drain electrode on a second side of the semiconductor channel, a polarization layer over the semiconductor channel, an insulator stack over the polarization layer, and a gate electrode over the semiconductor channel. In an embodiment, the gate electrode comprises a main body that passes through the insulator stack and the polarization layer, and a first field plate extending out laterally from the main body.

First claim

What is claimed is:

1. A transistor, comprising:
a semiconductor channel;
a source electrode on a first side of the semiconductor channel;
a drain electrode on a second side of the semiconductor channel;
a polarization layer over the semiconductor channel;
an insulator stack over the polarization layer, wherein the insulator stack comprises alternating layers of silicon nitride and oxide; and
a gate electrode over the semiconductor channel, wherein the gate electrode comprises:
a main body that passes through the insulator stack and into the polarization layer;
a first field plate extending out laterally from the main body; and
a second field plate extending out laterally from the main body, the second field plate vertically over the first field plate, wherein the first field plate extends laterally beyond the second field plate, and wherein the first field plate is positioned in a first oxide layer of the insulator stack and the second field plate is positioned in a second oxide layer of the insulator stack.

2. The transistor of claim 1 , wherein the first field plate extends out laterally towards the drain electrode.

3. The transistor of claim 2 , further comprising a third field that extends out laterally towards the source electrode.

4. The transistor of claim 1 , wherein the first oxide layer is a different oxide than the second oxide layer.

5. The transistor of claim 1 , further comprising a gate oxide surrounding gate electrode, wherein the gate oxide surrounds the main body and the first field plate.

6. A transistor, comprising:
a semiconductor channel;
a source electrode on a first side of the semiconductor channel;
a drain electrode on a second side of the semiconductor channel;
a polarization layer over the semiconductor channel;
an insulator stack over the polarization layer, wherein the insulator stack comprises a non-uniform etch selectivity in the thickness direction; and
a gate electrode over the semiconductor channel, wherein the gate electrode comprises:
a first portion into the polarization layer, wherein the first portion has a first width; and
a second portion passing through the insulator stack, wherein the second portion includes a stepped profile comprising a first field plate extending out laterally from the first portion, and a second field plate extending out laterally from the first portion, the second field plate vertically over the first field plate, wherein the first field plate extends laterally beyond the second field plate.

7. The transistor of claim 6 , wherein the stepped profile is symmetric about a centerline of the second portion.

8. The transistor of claim 6 , wherein the insulator stack comprises a plurality of layers of silicon nitride, wherein the layers have different etch rates.

9. The transistor of claim 8 , wherein the silicon nitride layers are treated with different plasma treatments to provide the different etch rates.

10. A method of forming a transistor, comprising:
providing a semiconductor channel, a source electrode on a first side of the semiconductor channel, a drain electrode on a second side of the semiconductor channel, a polarization layer over the semiconductor channel, and an insulator stack over the polarization layer;
forming a gate electrode opening through the insulator stack and into the polarization layer, wherein the gate opening has a first width;
forming a field plate opening in the insulator stack;
forming a gate oxide over surfaces of the gate electrode opening and the field plate opening; and
depositing a conductive layer into the gate electrode opening and the field plate opening to form a gate electrode, wherein the gate electrode comprises a main body that passes through the insulator stack and into the polarization layer, a first field plate extending out laterally from the main body, and a second field plate extending out laterally from the main body, the second field plate vertically over the first field plate, wherein the first field plate extends laterally beyond the second field plate.

11. The method of claim 10 , wherein the insulator stack comprises alternating layers of silicon nitride and oxide, wherein the field plate opening is formed in a first oxide layer.

12. The method of claim 11 , wherein the insulator stack further comprises a second oxide layer, wherein the first oxide layer and the second oxide layer have different etch rates.

13. A computing system, comprising:
a motherboard;
a processor electrically coupled to the motherboard; and
a communication chip electrically coupled to the motherboard, wherein one or both of the processor and the communication chip comprise a transistor, comprising:
a semiconductor channel;
a source electrode on a first side of the semiconductor channel;
a drain electrode on a second side of the semiconductor channel;
a polarization layer over the semiconductor channel;
an insulator stack over the polarization layer, wherein the insulator stack comprises alternating layers of silicon nitride and oxide; and
a gate electrode over the semiconductor channel, wherein the gate electrode comprises:
a main body that passes through the insulator stack and into the polarization layer;
a first field plate extending out laterally from the main body; and
a second field plate extending out laterally from the main body, the second field plate vertically over the first field plate, wherein the first field plate extends laterally beyond the second field plate, and wherein the first field plate is positioned in a first oxide layer of the insulator stack and the second field plate is positioned in a second oxide layer of the insulator stack.

14. The computing system of claim 13 , wherein the computing system is a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder.

15. A transistor, comprising:
a semiconductor channel;
a source electrode on a first side of the semiconductor channel;
a drain electrode on a second side of the semiconductor channel;
a polarization layer over the semiconductor channel;
an insulator stack over the polarization layer; and
a gate electrode over the semiconductor channel, wherein the gate electrode comprises:
a main body that passes through the insulator stack and into the polarization layer;
a first field plate extending out laterally from the main body;
a second field plate extending out laterally from the main body, the second field plate vertically over the first field plate, wherein the first field plate extends laterally beyond the second field plate; and
a gate oxide surrounding gate electrode, wherein the gate oxide surrounds the main body and the first field plate.

Assignees

• Intel Corp

Inventors

• Ramaswamy Rahul
• Nidhi Nidhi
• Hafez Walid M
• Rode Johann C
• Fischer Paul
• Then Han Wui
• Radosavljevic Marko
• Dasgupta Sansaptak
• Vora Heli Chetanbhai

Classifications

• H10P14/3416

  Nitrides · CPC title

• H10P14/3216

  Nitrides · CPC title

• H10D64/0116

  to Group III-V semiconductors · CPC title

• H10D64/256

  for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673) · CPC title

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title