Integrated assemblies and methods of forming integrated assemblies

Patent metadata

Field	Value
Publication number	US-11626488-B2
Application number	US-202117453621-A
Country	US
Kind code	B2
Filing date	Nov 4, 2021
Priority date	Aug 27, 2020
Publication date	Apr 11, 2023
Grant date	Apr 11, 2023

Abstract

Some embodiments include a transistor having an active region containing semiconductor material. The semiconductor material includes at least one element selected from Group 13 of the periodic table in combination with at least one element selected from Group 16 of the periodic table. The active region has a first region, a third region offset from the first region, and a second region between the first and third regions. A gating structure is operatively adjacent to the second region. A first carrier-concentration-gradient is within the first region, and a second carrier-concentration-gradient is within the third region. Some embodiments include methods of forming integrated assemblies.

First claim

We claim:

1. A transistor comprising:
an active region comprising semiconductor material; the active region comprising a first region, a third region offset from the first region, and a second region between the first and third regions; the first region having an inner edge adjacent the second region and an outer edge distal from the second region; the third region having an inner edge adjacent the second region and an outer edge distal from the second region;
a gating structure operatively adjacent the second region;
a first carrier-concentration-gradient within the first region, the first carrier-concentration-gradient increasing along a direction from the inner edge of the first region to the outer edge of the first region; and
a second carrier-concentration-gradient within the third region, the second carrier-concentration-gradient increasing along a direction from the inner edge of the third region to the outer edge of the third region.

2. The transistor of claim 1 wherein the third region is vertically offset from the first region.

3. The transistor of claim 1 wherein the third region is about a same length as the first region.

4. The transistor of claim 1 wherein the third region is a different length than the first region.

5. The transistor of claim 1 wherein the first and second carrier-concentration-gradients are continuous gradients.

6. The transistor of claim 1 wherein the first and second carrier-concentration-gradients are step gradients.

7. The transistor of claim 1 wherein the semiconductor material comprises indium, gallium and zinc.

8. The transistor of claim 1 wherein the second region has a first edge adjacent the first region, a second edge adjacent the third region, and an internal region between the first and second edges; and further comprising a third carrier-concentration-gradient within the second region; the third carrier-concentration-gradient decreasing from the first edge to the internal region, and increasing from the internal region to the second edge.

9. The transistor of claim 1 wherein the semiconductor material is a semiconductor oxide material.

10. The transistor of claim 1 comprising gate dielectric material between the gating structure and the second region, and being configured to alleviate hot carrier degradation of the gate dielectric material.

11. The transistor of claim 1 comprising a threshold voltage associated with the second region, and being configured to alleviate age-induced increase of the threshold voltage.

12. An integrated assembly comprising an access device between a storage element and a conductive structure; the access device comprising:
an active region comprising semiconductor material; the active region comprising a first region, a third region offset from the first region, and a second region between the first and third regions; the first region having an inner edge adjacent the second region and an outer edge distal from the second region; the third region having an inner edge adjacent the second region and an outer edge distal from the second region;
a gating structure operatively adjacent the second region;
a first carrier-concentration-gradient within the first region, the first carrier-concentration-gradient increasing along a direction from the inner edge of the first region to the outer edge of the first region; and
a second carrier-concentration-gradient within the third region, the second carrier-concentration-gradient increasing along a direction from the inner edge of the third region to the outer edge of the third region.

13. The integrated assembly of claim 12 wherein the access device further comprises:
a first oxygen-depleted-region outward of the first region;
a second oxygen-depleted-region outward of the third region;
a first conductive-metal-oxide outward of the first oxygen-depleted-region and electrically coupled with the conductive structure; and
a second conductive-metal-oxide outward of the second oxygen-depleted-region and electrically coupled with the storage element.

14. The integrated assembly of claim 13 wherein the semiconductor material comprises indium, gallium, zinc and oxygen.

15. The integrated assembly of claim 14 wherein the first and second carrier-concentration-gradients are associated with changes in a relative concentration of zinc within the first and third regions; the relative concentration of zinc being higher in regions having higher carrier concentration than in regions having lower carrier concentration.

16. The integrated assembly of claim 14 wherein the first and second carrier-concentration-gradients are associated with changes in a relative concentration of indium within the first and third regions; the relative concentration of indium being higher in regions having higher carrier concentration than in regions having lower carrier concentration.

17. The integrated assembly of claim 14 further comprising one or both of carbon and boron with the first, second and third regions.

18. The integrated assembly of claim 12 wherein the conductive structure is a first linear structure and is coupled with sensing circuitry, and wherein the gating structure is part of a second linear structure which is coupled with driver circuitry.

19. The integrated assembly of claim 12 wherein the storage element and the access device are within a memory cell, and wherein the memory cell is one of many substantially identical memory cells of a memory array.

20. A method of forming an integrated assembly, comprising:
forming a structure comprising semiconductor material; the structure having a second region offset from a first region; the first region having an inner edge adjacent the second region and having an outer edge distal from the second region;
incorporating a modifier material into the semiconductor material, the modifier material comprising one or both of carbon and boron and being provided in a concentration gradient which increases from the outer edge to the inner edge; and
subjecting the semiconductor material to reducing conditions to impose a carrier-concentration-gradient into the semiconductor material, the carrier-concentration-gradient being substantially inverse to the concentration gradient of the modifier material.

21. The method of claim 20 wherein the semiconductor material comprises indium, gallium, zinc and oxygen.

Assignees

• Micron Technology Inc

Inventors

• Pulugurtha Srinivas
• Guha Jaydip
• Sills Scott E
• Lee Yi Fang

Classifications

• H10D84/811

  Combinations of field-effect devices and one or more diodes, capacitors or resistors · CPC title

• H10D84/0128

  Manufacturing their channels · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D62/80

  characterised by the materials · CPC title

• H10D30/6728

  Vertical TFTs · CPC title