Buried grid with shield in wide band gap material

Patent metadata

Field	Value
Publication number	US-11626478-B2
Application number	US-201917055686-A
Country	US
Kind code	B2
Filing date	May 22, 2019
Priority date	May 22, 2018
Publication date	Apr 11, 2023
Grant date	Apr 11, 2023

Abstract

There is disclosed a structure in a wide band gap material such as silicon carbide wherein there is a buried grid and shields covering at least one middle point between two adjacent parts of the buried grid, when viewed from above. Advantages of the invention include easy manufacture without extra lithographic steps compared with standard manufacturing process, an improved trade-off between the current conduction and voltage blocking characteristics of a JBSD comprising the structure.

First claim

The invention claimed is:

1. A method of designing a structure for a wide band gap material, said method comprising the steps of:
designing a layer comprising a buried grid and spaces, the layer being composed of a first doped type of wide band gap material of a first conductivity type, the buried grid being composed of a second doped type of the wide band gap material of a second conductivity type, the second conductivity type being opposite to the first conductivity type, the buried grid being foraminous and comprising a plurality of parts in a regularly spaced pattern separated by spaces of the first doped wide band gap material;
calculating an electric field around the buried grid assuming that a voltage potential difference occurs over the layer; and
positioning shields where the electric field exceeds a defined value in a plane above the layer, the shields spaced in a pattern separated by separations of the first doped wide band gap material, the shields covering at least a middle point in the space between adjacent ones of the parts of the buried grid.

2. The method according to claim 1 , comprising designing the structure as a junction barrier Schottky diode.

3. The method according to claim 1 , wherein the method is implemented on a computer.

4. The method according to claim 1 , comprising designing the structure according to claim 1 .

5. A structure for use between conducting layers to which a voltage is applied, the structure comprising:
a layer disposed between the conducting layers and being composed of a first doped type of wide band gap material of a first conductivity type;
a buried grid disposed on a first plane in the layer and being composed of a second doped type of the wide band gap material of a second conductivity type, the second conductivity type being opposite to the first conductivity type, the buried grid being foraminous and comprising a plurality of parts in a regularly spaced pattern separated by spaces of the first doped wide band gap material; and
a shielding disposed in a second plane parallel with the first plane of the layer, the shielding having one or more regions spaced in a pattern separated by separations of the first doped wide band gap material, the one or more regions of the shielding covering at least a middle point in the space between adjacent ones of the parts of the buried grid.

6. The structure of claim 5 , the voltage applied between the conducting layers between which the layer is disposed producing an electric field, wherein the one or more regions of the shielding cover the middle point where the electrical field reaches a maximum.

7. The structure of claim 5 , wherein the one or more regions of the shielding cover at least the middle point of a straight line between the adjacent ones of the parts of the buried grid.

8. The structure of claim 5 , wherein the shielding is positioned above the layer.

9. The structure of claim 5 , wherein the shielding is at least partially positioned in the layer and is disposed apart from contact with the buried grid.

10. The structure of claim 5 , wherein the shielding comprises an insulating material.

11. The structure of claim 5 , wherein the shielding comprises a third doped type of the wide band gap material of the same second conductivity type as the buried grid.

12. The structure of claim 5 , wherein the shielding is foraminous.

13. The structure of claim 5 , wherein at least one ohmic contact is disposed on the shielding.

14. The structure of claim 5 , wherein a smallest size of any one of the one or more regions of the shielding in any direction in the second plane is in an interval 0.3 to 5 μm.

15. The structure of claim 5 , wherein a height of any of the one or more regions of the shielding measured perpendicular to the layer is at least 20 nm.

16. The structure of claim 5 , wherein a height of the buried grid measured perpendicular to the layer is in an interval of 0.3 to 2 μm.

17. The structure of claim 5 , wherein a smallest size of any one of the parts of the buried grid in any direction in the first plane is in an interval of 0.3 to 4 μm.

18. The structure of claim 5 , wherein a smallest size of each of the spaces in any direction in the first plane is in an interval of 0.3 to 10 μm.

19. The structure of claim 5 , wherein the wide band gap material is selected from the group consisting of silicon carbide, diamond, gallium oxide, and gallium nitride.

20. The structure of claim 5 , wherein the structure has been manufactured in a process comprising epitaxial growth of the wide band gap material.

21. A junction barrier Schottky diode comprising the structure according to claim 5 .

Assignees

• Ascatron Ab
• Ii Vi Delaware Inc

Inventors

• Elahipanah Hossein

Classifications

• H10D64/112

  comprising multiple field plate segments · CPC title

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title

• H10D62/8325

  Silicon carbide · CPC title

• H10D62/8303

  Diamond · CPC title

• H10D62/80

  characterised by the materials · CPC title