Integration of a Schottky diode with a MOSFET

Patent metadata

Field	Value
Publication number	US-11114557-B2
Application number	US-201816647186-A
Country	US
Kind code	B2
Filing date	Sep 14, 2018
Priority date	Sep 15, 2017
Publication date	Sep 7, 2021
Grant date	Sep 7, 2021

Abstract

There is disclosed the integration of a Schottky diode with a MOSFET, more in detail there is a free-wheeling Schottky diode and a power MOSFET on top of a buried grid material structure. Advantages of the specific design allow the whole surface area to be used for MOSFET and Schottky diode structures, the shared drift layer is not limited by Schottky diode or MOSFET design rules and therefore, one can decrease the thickness and increase the doping concentration of the drift layer closer to a punch through design compared to the state of the art. This results in higher conductivity and lower on-resistance of the device with no influence on the voltage blocking performance. The integrated device can operate at higher frequency. The risk for bipolar degradation is avoided.

First claim

The invention claimed is:

1. A device comprising the following parts:
a n-type substrate;
a n-type drift epitaxial layer on the n-type substrate;
a n-type epitaxial regrown layer on the n-type drift epitaxial layer;
a p-type grid layer comprising a grid in the n-type drift epitaxial layer and in contact with the n-type epitaxial regrown layer;
a p-type feeder layer in the n-type drift epitaxial layer and in contact with the n-type epitaxial regrown layer, the grid layer and the p-type feeder layer are connected;
an ohmic contact applied at least partially on the p-type feeder layer;
a metallization layer;
a MOSFET structure having:
a p-well region;
a n+ source region;
a gate oxide;
a source ohmic contact;
the ohmic contact is connected to the source ohmic contact through the metallization layer;
the p-well region is arranged so that it is in contact with the n-type epitaxial regrown layer, the n+ source region, the gate oxide, and the source ohmic contact;
the n+ source region is arranged so that it is in contact with the p-well region, the gate oxide, and the source ohmic contact;
a gate contact; and
an isolation layer for gate contact area insulation from the metallization layer, the gate oxide is in contact with the p-well region, the n+ source region, the gate contact, and the isolation layer;
the gate oxide is in contact with the n-type epitaxial regrown layer and the source ohmic contact;

a Schottky contact, the metallization layer applied at least partially on the device and in contact with the Schottky contact, and the Schottky contact in contact with the n-type epitaxial regrown layer; and
a drain ohmic contact and a metallization.

2. The device according to claim 1 , wherein the device comprises a n+-type epitaxial buffer layer between the n-type substrate and the n-type drift epitaxial layer.

3. The device according to claim 1 , wherein the device comprises a JFET region in contact with the n-type epitaxial regrown layer, the p-well region, and the gate oxide.

4. The device according to claim 1 , wherein the p-well region comprises an implanted layer.

5. The device according to claim 1 , wherein the p-well region comprises an epitaxial layer.

6. The device according to claim 1 , wherein the n+ source region comprises an implanted layer.

7. The device according to claim 1 , wherein the n+ source region comprises an epitaxial layer.

8. The device according to claim 1 , wherein the gate contact comprises polysilicon.

9. The device according to claim 1 , wherein the Schottky contact comprises a metal.

10. The device according to, claim 1 wherein the Schottky contact comprises polysilicon.

11. The device according to claim 1 , wherein the p-type grid layer comprises a plurality of grids, wherein at least a part of the grids has a ledge positioned centered under the grid, the ledge positioned towards the n-type substrate, said ledge having a smaller lateral dimension than the grid.

12. The device according to claim 1 , wherein the p-type grid layer comprises a plurality of grids, wherein each grid comprises an upper part and a lower part said lower part is towards the n-type substrate; wherein the upper part is manufactured using epitaxial growth; and wherein the lower part is manufactured using ion implantation.

13. The device according to claim 1 , wherein the n-type epitaxial regrown layer comprises at least two n-type epitaxial regrown layers with different doping levels and thickness as either a drift layer or a current spreading layer.

14. The device according to claim 13 , wherein the n-type epitaxial regrown layer closest to the p-type grid layer has a higher doping concentration compared to the n-type epitaxial regrown layer furthest away from the p-type grid layer.

15. The device according to claim 13 , wherein the n-type epitaxial regrown layer closest to the p-type grid layer has a lower doping concentration compared to the n-type epitaxial regrown layer furthest away from the p-type grid layer.

16. The device according to claim 13 , wherein the n-type epitaxial regrown layer has a gradient in the doping concentration.

17. The device according to claim 16 , wherein the doping concentration in the n-type epitaxial regrown layer is lower closest to the p-type grid layer and furthest away from the p-type grid layer compared to the middle part of the n-type epitaxial regrown layer.

18. The device according to claim 1 , wherein the p-type grid layer has a first repeating structure in at least a first direction, wherein the first repeating structure repeats with a first regular distance in at least the first direction, and wherein the MOSFET structure and the Schottky contact have a second repeating structure in at least a second direction, wherein the second repeating structure repeats with a second regular distance in at least the second direction.

19. The device according to claim 18 , wherein along any possible defined direction, a first distance between the first repeating structures of the p-type grid layer is not the same as the second distance between the second repeating structures of the MOSFET structure and the Schottky contact, the first and second distances measured along the same direction.

20. The device according to claim 1 , wherein the MOSFET structure and the Schottky contact are repeated alternatingly where a Schottky contact is between every MOSFET structure.

21. The device according to claim 1 , wherein there is at least one epitaxially grown p-type region in contact with the ohmic contact, wherein the p-type feeder layer comprises at least one region for each epitaxially grown p-type region, wherein a projection of the epitaxially grown p-type region in a plane parallel with the n-type substrate has a boundary line limiting the projection of the epitaxially grown p-type region, wherein the p-type feeder layer is applied at least so that a projection of the p-type feeder layer in a plane parallel to the n-type substrate is in a surrounding of the boundary line, so that the distance from the boundary line to any point in the surrounding is maximum 0.5 μm and wherein the p-type feeder layer also is applied so that the distance from the lower part of the epitaxially grown p-type region to the upper part of the p-type feeder layer is in the range 0-5 μm, the direction up is given by the direction perpendicular away from the n-type substrate.

Assignees

• Ii Vi Delaware Inc

Inventors

• Thierry-Jebali Nicolas
• Elahipanah Hossein
• Schöner Adolf
• Reshanov Sergey

Classifications

• H10D8/60 Primary

  Schottky-barrier diodes · CPC title

• H10D30/66

  Vertical DMOS [VDMOS] FETs · CPC title

• H10D84/146 Primary

  the built-in components being Schottky barrier diodes · CPC title

• H10D84/811

  Combinations of field-effect devices and one or more diodes, capacitors or resistors · CPC title

• H10D64/64

  Electrodes comprising a Schottky barrier to a semiconductor · CPC title