Semiconductor package with barrier to contain thermal interface material

Patent metadata

Field	Value
Publication number	US-11626351-B2
Application number	US-202117158234-A
Country	US
Kind code	B2
Filing date	Jan 26, 2021
Priority date	Jan 26, 2021
Publication date	Apr 11, 2023
Grant date	Apr 11, 2023

Abstract

A semiconductor package includes a semiconductor die, an encapsulant body of electrically insulating material that encapsulates the semiconductor die, a thermal conduction plate comprising an outer surface that is exposed from the encapsulant body, a region of thermal interface material interposed between the thermal conduction plate and the semiconductor die, the region of thermal interface material being a liquid or semi-liquid, and a barrier that is configured to prevent the thermal interface material of the region from flowing laterally across the barrier.

First claim

What is claimed is:

1. A semiconductor package, comprising:
a semiconductor die;
an encapsulant body of electrically insulating material that encapsulates the semiconductor die;
a thermal conduction plate comprising an outer surface that is exposed from the encapsulant body;
a region of thermal interface material interposed between the thermal conduction plate and the semiconductor die, the region of thermal interface material being a liquid or semi-liquid; and
a barrier that is configured to prevent the thermal interface material of the region from flowing laterally across the barrier,
wherein the region of thermal interface material is disposed exclusively on one side of the thermal conduction plate,
wherein the encapsulant body comprises a main surface, a rear surface opposite the main surface, and outer edge surfaces extending between the main surface and the rear surface,
wherein the barrier comprises an inner wall that extends transversely to the main surface and faces the thermal interface material, and
wherein the barrier comprises an electrically insulating structure that is separate from the encapsulant body.

2. The semiconductor package of claim 1 , wherein the barrier is configured so that the inner wall forms an enclosed loop around the region of thermal interface material.

3. The semiconductor package of claim 1 , wherein the barrier comprises a recess formed in the main surface of the encapsulant body, wherein the inner wall of the barrier comprises a sidewall of the recess, and wherein the region of thermal interface material is completely disposed below the main surface of the encapsulant body.

4. The semiconductor package of claim 1 , wherein the semiconductor package further comprises a die pad, wherein the semiconductor die is mounted on the die pad, wherein a rear surface of the die pad that is opposite from the semiconductor die is exposed from the encapsulant body, and wherein the region of thermal interface material directly interfaces with the thermal conduction plate and the rear surface of the die pad.

5. The semiconductor package of claim 1 , wherein the thermal interface material comprises an electrically insulating liquid matrix and one or both of: metal particles suspended in the liquid matrix, and metal wires suspended in the liquid matrix.

6. The semiconductor package of claim 5 , wherein the metal particles and/or metal wires are coated with an electrically insulating material.

7. The semiconductor package of claim 1 , wherein the thermal conduction plate is sintered body of ceramic material comprising any one or combination of a nitride ceramic, an oxide ceramic, a silicate ceramic, and a carbide material.

8. The semiconductor package of claim 1 , wherein the thermal conduction comprises an organic insulation material.

9. A method of producing a semiconductor package, the method comprising:
providing a semiconductor die;
forming an encapsulant body of electrically insulating material that encapsulates the semiconductor die;
forming a barrier;
providing a thermal interface material that is liquid or semi-liquid;
providing a thermal conduction plate that is electrically insulating and thermally conductive; and
arranging the thermal conduction plate on the semiconductor package such that a first region of the thermal interface material is interposed between the thermal conduction plate and the semiconductor die, and
wherein after the arranging the barrier is configured to prevent thermal interface material of the first region from flowing laterally across the barrier, and
wherein after the arranging the region of thermal interface material is disposed exclusively on one side of the thermal conduction plate,
wherein the barrier is formed as an integrally formed feature of the encapsulant body,
wherein the encapsulant body is formed by performing a first molding process, and wherein the barrier is formed by performing a second molding process that is separate from first molding process.

10. The method of claim 9 , wherein arranging the thermal conduction plate on the semiconductor package comprises pre-coating a surface of the semiconductor package that is thermally coupled to the semiconductor die with the thermal interface material and subsequently placing the thermal conduction plate on top of the thermal interface material.

11. The method of claim 9 , wherein arranging the thermal conduction plate on the semiconductor package comprises pre-coating a surface of the thermal conduction plate with the thermal interface material and subsequently placing the thermal conduction plate on a surface of the semiconductor package that is thermally coupled to the semiconductor die.

12. The method of claim 9 , further comprising forming a second region of the thermal interface material over an outer surface of the thermal conduction plate that faces away from the encapsulant body after arranging the thermal conduction plate on the semiconductor package.

13. The method of claim 9 , wherein after the arranging the region of thermal interface material either the thermal conduction plate is disposed completely outside of the encapsulant body or the thermal conduction plate is disposed with a recess of the encapsulant body with outer edge sides of the thermal conduction plate directly contacting the encapsulant body.

14. A semiconductor package, comprising:
a semiconductor die;
an encapsulant body of electrically insulating material that encapsulates the semiconductor die;
a thermal conduction plate comprising an outer surface that is exposed from the encapsulant body;
a region of thermal interface material interposed between the thermal conduction plate and the semiconductor die, the region of thermal interface material being a liquid or semi-liquid; and
a barrier that is configured to prevent the thermal interface material of the region from flowing laterally across the barrier,
wherein the encapsulant body comprises a main surface,
wherein the barrier comprises an inner wall that extends transversely to the main surface and faces the thermal interface material,
wherein the barrier comprises a protrusion of the encapsulant body that extends above the main surface,
wherein the inner wall of the barrier is a sidewall of the protrusion, and
wherein the thermal conduction plate is mounted on top of the protrusion.

15. A method of producing a semiconductor package, the method comprising:
providing a semiconductor die;
forming an encapsulant body of electrically insulating material that encapsulates the semiconductor die;
forming a barrier;
providing a thermal interface material that is liquid or semi-liquid;
providing a thermal conduction plate that is electrically insulating and thermally conductive; and
arranging the thermal conduction plate on the semiconductor package such that a first region of the thermal interface material is interposed between the thermal conduction plate and the semiconductor die,
wherein the barrier comprises an inner wall that extends transversely to the main surface and faces the thermal interface material,
wherein the encapsulant body comprises a main surface,
wherein the barrier comprises a protrusion of the encapsulant body that extends above the main surface,
wherein the inner wall of the barrier is a sidewall of the protrusion, and
wherein the thermal conduction plate is mounted on top of the protrusion,
wherein after the arranging the barrier is configured to prevent thermal interface material of the first region from flowing laterally across the barrier.

Assignees

• Infineon Technologies Ag

Inventors

• Nikitin Ivan
• Bohnenberger Timo
• Grassmann Andreas
• Mayer Martin
• Roth Alexander
• Zollner Franz

Classifications

• H10W90/00

  Package configurations · CPC title

• H10W74/129

  forming a chip-scale package [CSP] · CPC title

• H10W74/111

  the semiconductor body being completely enclosed · CPC title

• H10W74/016

  using moulds · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title