Radio frequency silicon on insulator structure with superior performance, stability, and manufacturability

Patent metadata

Field	Value
Publication number	US-11626318-B2
Application number	US-202117234023-A
Country	US
Kind code	B2
Filing date	Apr 19, 2021
Priority date	Jul 13, 2018
Publication date	Apr 11, 2023
Grant date	Apr 11, 2023

Abstract

A semiconductor-on-insulator (e.g., silicon-on-insulator) structure having superior radio frequency device performance, and a method of preparing such a structure, is provided by utilizing a single crystal silicon handle wafer sliced from a float zone grown single crystal silicon ingot.

First claim

What is claimed is:

1. A multilayer structure comprising:
a single crystal silicon wafer handle substrate comprising two major, generally parallel surfaces, one of which is a front surface of the single crystal silicon wafer handle substrate and the other of which is a back surface of the single crystal silicon wafer handle substrate, a circumferential edge joining the front and back surfaces of the single crystal silicon wafer handle substrate, and a central plane of the single crystal silicon wafer handle substrate between the front and back surfaces of the single crystal silicon wafer handle substrate, wherein the single crystal silicon wafer handle substrate has a bulk resistivity of at least about 5000 ohm-cm, an interstitial oxygen concentration of less than about 1×10 16 atoms/cm 3 , and a nitrogen concentration of at least about 1×10 13 atoms/cm 3 ;
a trap rich layer in interfacial contact with the front surface of the single crystal silicon wafer handle substrate;
a dielectric layer in interfacial contact with the trap rich layer; and
a single crystal semiconductor device layer in interfacial contact with the dielectric layer;
wherein the multilayer structure demonstrates a second harmonic distortion, HD 2 , value better than −90 dBm at a radiofrequency input power of 15 dBm.

2. The multilayer structure of claim 1 wherein the single crystal silicon wafer handle substrate comprises a silicon wafer sliced from a single crystal silicon ingot grown by a float zone method.

3. The multilayer structure of claim 2 wherein the silicon wafer sliced from a single crystal silicon ingot grown by the float zone method has a diameter of at least about 150 mm.

4. The multilayer structure of claim 2 wherein the silicon wafer sliced from a single crystal silicon ingot grown by the float zone method has a diameter of at least about 200 mm.

5. The multilayer structure of claim 1 wherein the single crystal silicon wafer handle substrate has a bulk resistivity of at least about 10,000 ohm-cm.

6. The multilayer structure of claim 1 wherein the single crystal silicon wafer handle substrate has a bulk resistivity of at least about 15,000 ohm-cm.

7. The multilayer structure of claim 1 wherein the single crystal silicon wafer handle substrate has a bulk resistivity of at least about 20,000 ohm-cm.

8. The multilayer structure of claim 1 wherein the single crystal silicon wafer handle substrate has a bulk resistivity of less than about 100,000 ohm-cm.

9. The multilayer structure of claim 1 wherein the single crystal silicon wafer handle substrate has an excess thermal donor concentration of less than 1×10 11 donors/cm 3 .

10. The multilayer structure of claim 1 wherein the single crystal silicon wafer handle substrate has an excess thermal donor concentration of less than 5×10 10 donors/cm 3 .

11. The multilayer structure of claim 1 wherein the single crystal silicon wafer handle substrate comprises a p-type dopant at a concentration of less than 1×10 12 atoms/cm 3 and further wherein a concentration of oxygen thermal double donors, new donors, and excess thermal donors, or any combination thereof is at least an order of magnitude less than the concentration of the p-type dopant.

12. The multilayer structure of claim 1 wherein the single crystal silicon wafer handle substrate comprises a p-type dopant at a concentration of less than 1×10 11 atoms/cm 3 and further wherein a concentration of oxygen thermal double donors, new donors, and excess thermal donors, or any combination thereof is at least an order of magnitude less than the concentration of the p-type dopant.

13. The multilayer structure of claim 1 wherein the single crystal silicon wafer handle substrate comprises an n-type dopant at a concentration of less than 1×10 12 atoms/cm 3 and further wherein a concentration of oxygen thermal double donors, new donors, and excess thermal donors, or any combination thereof is at least an order of magnitude less than the concentration of the n-type dopant.

14. The multilayer structure of claim 1 wherein the single crystal silicon wafer handle substrate comprises an n-type dopant at a concentration of less than 1×10 11 atoms/cm 3 and further wherein a concentration of oxygen thermal double donors, new donors, and excess thermal donors, or any combination thereof is at least an order of magnitude less than the concentration of the n-type dopant.

15. The multilayer structure of claim 1 wherein the single crystal silicon wafer handle substrate has an interstitial oxygen concentration of less than about 1×10 15 atoms/cm 3 .

16. The multilayer structure of claim 1 wherein the single crystal silicon wafer handle substrate has a nitrogen concentration of at least about 1×10 14 atoms/cm 3 .

17. The multilayer structure of claim 1 wherein the single crystal silicon wafer handle substrate has a nitrogen concentration of less than about 3×10 15 atoms/cm 3 .

18. The multilayer structure of claim 1 wherein the single crystal silicon wafer handle substrate has a nitrogen concentration of less than about 1×10 15 atoms/cm 3 .

19. The multilayer structure of claim 1 wherein the single crystal silicon wafer handle substrate has a nitrogen concentration of less than about 7×10 14 atoms/cm 3 .

20. The multilayer structure of claim 1 wherein the single crystal silicon wafer handle substrate has a nitrogen concentration between about 5×10 14 atoms/cm 3 and about 2×10 15 atoms/cm 3 .

21. The multilayer structure of claim 1 wherein the trap rich layer comprises one or more polycrystalline semiconductor layers, wherein each of the one or more polycrystalline semiconductor layers comprises a material selected from the group consisting of silicon, SiGe, SiC, and Ge.

22. The multilayer structure of claim 1 wherein the trap rich layer comprises one or more amorphous semiconductor layers, wherein each of the one or more amorphous semiconductor layers comprises a material selected from the group consisting of silicon, SiGe, SiC, and Ge.

23. The multilayer structure of claim 1 wherein the trap rich layer has a resistivity greater than about 1000 Ohm-cm.

24. The multilayer structure of claim 1 wherein the trap rich layer has a resistivity greater than about 3000 Ohm-cm.

25. The multilayer structure of claim 1 wherein the trap rich layer has a resistivity between about 2000 Ohm-cm and about 10,000 Ohm-cm.

26. The multilayer structure of claim 1 wherein the trap rich layer has a resistivity between about 3000 Ohm-cm and about 10,000 Ohm-cm.

27. The multilayer structure of claim 1 wherein the trap rich layer has a resistivity between about 3000 Ohm-cm and about 5,000 Ohm-cm.

28. The multilayer structure of claim 1 wherein the trap rich layer has a thickness between about 0.1 micrometer and about 50 micrometers.

29. The multilayer structure of claim 1 wherein the trap rich layer has a thickness between about 0.1 micrometer and about 20 micrometers.

30. The multilayer structure of claim 1 wherein the trap rich layer has a thickness between about 0.1 micrometer and about 10 micrometers.

31. The multilayer structure of claim 1 wherein the trap rich layer has a thickness between about 0.5 micrometer and about 5 micrometers.

32. The multilayer structure of claim 1 wherein the dielectric layer compris

Assignees

• Globalwafers Co Ltd

Inventors

• Seacrist Michael R
• Standley Robert W
• Libbert Jeffrey L
• Sreedharamurthy Hariprasad
• Jensen Leif

Classifications

• H10P90/1914

  using bonding · CPC title

• H10P36/07

  of silicon-on-insulator structures · CPC title

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10W44/241

  for passive devices or passive elements · CPC title

• H10W44/20

  at high-frequency [HF] or radio frequency [RF] · CPC title