Synthesis of a quantum circuit

Patent metadata

Field	Value
Publication number	US-11620563-B2
Application number	US-202117505308-A
Country	US
Kind code	B2
Filing date	Oct 19, 2021
Priority date	Jun 10, 2020
Publication date	Apr 4, 2023
Grant date	Apr 4, 2023

Abstract

Systems, computer-implemented methods, and computer program products to facilitate synthesis of a quantum circuit are provided. According to an embodiment, a system can comprise a memory that stores computer executable components and a processor that executes the computer executable components stored in the memory. The computer executable components can comprise a circuit generation component that generates, iteratively, quantum circuits from 1 to N two-qubit gates, wherein at least one or more iterations (1, 2, . . . , N) adds a single two-qubit gate to circuits from a previous iteration based on using added single 2-qubit gates that represent operations distinct from previous operations relative to previous iterations. The computer executable components can further comprise a circuit identification component that identifies, from the quantum circuits, a desired circuit that matches a quantum circuit representation.

First claim

What is claimed is:

1. A system, comprising:
a memory that stores computer executable components; and
a processor that executes the computer executable components stored in the memory, wherein the computer executable components comprise:
a circuit generation component that generates, during a first iteration, a first set of quantum circuits comprising 2-qubit gates;
a second circuit generation component that generates, during a second iteration, a second set of quantum circuits by adding a 2-qubit gate to the first set of quantum circuits such that the second set of quantum circuits are selected to a redundant operation use the 2-qubit gate without introducing the redundant operation to that of the first set of quantum circuits; and
a circuit identification component that identifies, from the first set of quantum circuits and the second set of quantum circuits, a desired circuit that matches a quantum circuit representation.

2. The system of claim 1 , wherein the first set of quantum circuits and the second set of quantum circuits comprise Clifford quantum circuits having a Clifford group, and wherein the computer executable components further comprise:
an interface component that receives the quantum circuit representation.

3. The system of claim 1 , wherein the first set of quantum circuits and the second set of quantum circuits comprise CNOT-Dihedral quantum circuits having a CNOT-Dihedral group.

4. The system of claim 1 , wherein the circuit generation component generates, iteratively, the first set of quantum circuits and the second circuit generation component generates, iteratively, the second set of quantum circuits to minimize a number of CNOT gates in the desired circuit.

5. The system of claim 1 , wherein the desired circuit comprises a defined number of CNOT gates and a Clifford quantum circuit having a Clifford group or a CNOT-Dihedral quantum circuit having a CNOT-Dihedral group.

6. The system of claim 5 , wherein the computer executable components further comprise:
an application component that performs randomized benchmarking on a defined number of qubits in a quantum device based on the desired circuit, thereby facilitating at least one of improved efficiency, improved performance, or reduced computational costs associated with at least one of the application component, the processor, or the system in performing the randomized benchmarking based on the desired circuit.

7. A computer-implemented method of synthesizing a quantum circuit, comprising:
generating, by a system operatively coupled to a processor, during a first iteration, a first set of quantum circuits comprising 2-qubit gates;
generating, by the system, during a second iteration, a second set of quantum circuits by adding a 2-qubit gate to the first set of quantum circuits such that the second set of quantum circuits are selected to a redundant operation use the 2-qubit gate without introducing the redundant operation to that of the first set of quantum circuits; and
identifying, by the system, from the first set of quantum circuits and the second set of quantum circuits, a desired circuit that matches a quantum circuit representation.

8. The computer-implemented method of claim 7 , wherein the first set of quantum circuits and the second set of quantum circuits comprise Clifford quantum circuits having a Clifford group, and further comprising:
receiving, by the system, the quantum circuit representation.

9. The computer-implemented method of claim 7 , wherein the first set of quantum circuits and the second set of quantum circuits comprise CNOT-Dihedral quantum circuits having a CNOT-Dihedral group.

10. The computer-implemented method of claim 7 , further comprising:
generating, by the system, iteratively, the first set of quantum circuits and the second set of quantum circuits to minimize a number of CNOT gates in the desired circuit.

11. The computer-implemented method of claim 7 , wherein the desired circuit comprises a defined number of CNOT gates and a Clifford quantum circuit having a Clifford group or a CNOT-Dihedral quantum circuit having a CNOT-Dihedral group.

12. The computer-implemented method of claim 11 , further comprising:
performing, by the system, randomized benchmarking on a defined number of qubits in a quantum device based on the desired circuit, thereby facilitating at least one of improved efficiency, improved performance, or reduced computational costs associated with at least one of the processor or the system in performing the randomized benchmarking based on the desired circuit.

Assignees

• IBM

Inventors

• Bravyi Sergey
• Cross Andrew W
• Garion Shelly-Erika
• Maslov Dmitri

Classifications

• G06N10/20 Primary

  Models of quantum computing, e.g. quantum circuits or universal quantum computers · CPC title

• G06F2119/02

  Reliability analysis or reliability optimisation; Failure analysis, e.g. worst case scenario performance, failure mode and effects analysis [FMEA] · CPC title

• G06F30/28

  using fluid dynamics, e.g. using Navier-Stokes equations or computational fluid dynamics [CFD] · CPC title

• G06F2111/02

  CAD in a network environment, e.g. collaborative CAD or distributed simulation · CPC title

• G06F30/392

  Floor-planning or layout, e.g. partitioning or placement · CPC title