Semiconductor digital logic circuitry for non-quantum enablement of quantum algorithms

Patent metadata

Field	Value
Publication number	US-2020192417-A1
Application number	US-201916553096-A
Country	US
Kind code	A1
Filing date	Aug 27, 2019
Priority date	Aug 28, 2018
Publication date	Jun 18, 2020
Grant date	—

Abstract

Circuitry and processes are disclosed that use conventional electronic circuits (comprising, for example, phase locked loops, pulse width modulators, phase modulators, digital logic gates, etc.) to enable quantum algorithms. Such circuitry and processes achieve the requirement for non-quantum devices to enable quantum algorithms: the tensor product entanglement of signals representing quantum states. Such circuitry and processes are readily usable by current Electronic Design Automation tools, to design, verify and emulate applications such as fast, very large number factoring for use in decryption. Also, the independent Claims concisely signify embodiments of the claimed inventions.

First claim

What is claimed:

1 . A more efficient/useful electronic structure for enabling an electronic circuit to act as a quantum qubit, comprising: an electronic circuit that generates two clock signals, where the time-dependence of the clock signals depend on a parameter, P 0 , that represents the probability that the clock signal is in a voltage state that represents a qubit being in one of its two basis states; on two parameters ϕ 0 and ϕ 1 that represent initial and transformed phases of the clocks signals that correspond to the phase shifts experienced by qubits in quantum computers; and on two unequal frequencies f 0 and f 1 which represent frequencies of the clock signals, wherein high frequencies selected for f 0 and f 1 allow more sampling of the final states of the qubits to be performed.

2 . The structure, process or circuit of claim 1 , applied usefully in commerce by enabling the electronic structure in an article of manufacture comprising one or more modules for transforming information, where the article of manufacture is either mostly structured by a manufacturer, structured, at least in part, by a user, or structured by both the manufacturer and the user; and equivalent articles of manufacture enabling the electronic structure.

3 . A quantum computing system comprising a semiconductor circuit configured to generate:
a first clock signal having a first frequency and a first duty cycle, said first clock signal defining a first state of a first qubit of the computing system; and a second clock signal having a second frequency and a second duty cycle, said second clock signal defining a second state of the first qubit, wherein a sum of the first and second duty cycles is one.

4 . The quantum computing system of claim 3 wherein said semiconductor circuit is further configured to generate:
a third clock signal having a third frequency and a third duty cycle, said third clock signal defining a first state of a second qubit of the computing system; and
a fourth clock signal having a fourth frequency and a fourth duty cycle, said fourth clock signal defining a second state of the second qubit, wherein a sum of the third and fourth duty cycles is one.

5 . The quantum computing system of claim 4 further comprising one or more phase locked loops adapted to generate the first, second, third and fourth clock signals.

6 . The quantum computing system of claim 5 further comprising:
a counter adapted to measure a state of the first qubit.

7 . A method of performing a numerical or logical operation, the method comprising:
submitting a request for the operation to a quantum computing system via a network, said quantum computing system comprising a semiconductor circuit configured to generate a first clock signal having a first frequency and a first duty cycle and a second clock signal having a second frequency and a second duty cycle, said first and second clock signals respectively representing first and second states of a first qubit of the quantum computing system; and receiving a result of the operation from the quantum computing system.

8 . The method of claim 7 wherein said quantum computing system is further configured to generate a third clock signal having a third frequency and a third duty cycle and a fourth clock signal having a fourth frequency and a fourth duty cycle, said third and fourth clock signals respectively representing first and second states of a second qubit of the quantum computing system.

9 . The method of claim 8 wherein said quantum computing system further comprises one or more phase locked loops adapted to generate the first, second, third and fourth clock signals.

10 . The method of claim 8 wherein said quantum computing system further comprises a counter adapted to measure a state of the first qubit.

Assignees

• Synopsys Inc

Inventors

• Fernandes Ramos Hugo Miguel

Classifications

• G06N7/01

  Probabilistic graphical models, e.g. probabilistic networks · CPC title

• G06F1/06 Primary

  Clock generators producing several clock signals {(G06F1/08 - G06F1/14 take precedence)} · CPC title

• B82Y10/00

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

• H03L7/0995

  the oscillator comprising a ring oscillator · CPC title

• H03L7/18

  using a frequency divider or counter in the loop (H03L7/20, H03L7/22 take precedence) · CPC title