Directed interrupt for multilevel virtualization with interrupt table

Patent metadata

Field	Value
Publication number	US-11620244-B2
Application number	US-202117482192-A
Country	US
Kind code	B2
Filing date	Sep 22, 2021
Priority date	Feb 14, 2019
Publication date	Apr 4, 2023
Grant date	Apr 4, 2023

Abstract

An interrupt signal is provided to a first guest operating system. A bus attachment device receives an interrupt signal from a bus connected module with an interrupt target ID identifying a processor assigned for use by the guest operating system as a target processor for handling the interrupt signal. The bus attachment device translates the received interrupt target ID to a logical processor ID of the target processor using an interrupt table entry stored in a memory section assigned to a second guest operating system hosting the first operating system and forwards the interrupt signal to the target processor for handling. The logical processor ID of the target processor is used to address the target processor directly.

First claim

What is claimed is:

1. A computer program product for providing an interrupt signal to a first guest operating system executed using one or more processors of a plurality of processors of a computer system, the computer program product comprising: one or more computer readable storage media and program instructions collectively stored on the one or more computer readable storage media to perform a method comprising: receiving the interrupt signal with an interrupt target ID, the interrupt target ID identifying one processor of the plurality of processors as a target processor to handle the interrupt signal, the one processor, at least, being assigned for usage by the first guest operating system, and wherein the interrupt target ID has a directed interrupt summary indicator assigned thereto to indicate that the interrupt signal is addressed to the interrupt target ID to be handled; retrieving a copy of an interrupt table entry assigned to the interrupt target ID from an interrupt table, the copy of the interrupt table entry comprising a mapping of the interrupt target ID to a logical processor ID; translating the interrupt target ID to the logical processor ID using the copy of the interrupt table entry; and forwarding the interrupt signal to the target processor to handle, the forwarding using the logical processor ID resulting from the translating to address the target processor directly.

2. The computer program product of claim 1 , wherein the interrupt table is stored in a first memory section of memory, the first memory section being assigned to a second guest operating system, the second guest operating system hosting the first guest operating system.

3. The computer program product of claim 2 , wherein the memory further comprises in a second memory section assigned to the first guest operating system a directed interrupt summary vector with a respective directed interrupt summary indicator per interrupt target ID, each respective directed interrupt summary indicator being assigned to a respective interrupt target ID to indicate whether there is a respective interrupt signal addressed to the respective interrupt target ID to be handled.

4. The computer program product of claim 3 , wherein the memory further comprises in the first memory section a forwarding vector comprising a first set of forwarding vector entries, the first set of forwarding vector entries comprising for each respective directed interrupt summary indicator of the directed interrupt summary vector a forwarding vector entry assigned to the respective directed interrupt summary indicator, each forwarding vector entry indicating whether the respective directed interrupt summary indicator to which it is assigned is to be updated in order to indicate for the first guest operating system that there is the respective interrupt signal addressed to the respective interrupt target ID to be handled.

5. The computer program product of claim 4 , wherein the method further comprises:
checking that the target processor is scheduled for usage by the first guest operating system; and
performing the translating and the forwarding, based on the target processor being scheduled for usage by the first guest operating system.

6. The computer program product of claim 5 , wherein the method further comprises forwarding the interrupt signal to the first guest operating system using broadcasting, based on the target processor not being scheduled for usage by the first guest operating system, the broadcasting comprising selecting a selected forwarding vector entry of the first set of forwarding vector entries which is assigned to the interrupt target ID and updating the selected forwarding vector entry such that it indicates that the respective directed interrupt summary indicator to which it is assigned is to be updated in order to indicate for the first guest operating system that there is the interrupt signal addressed to the interrupt target ID to be handled.

7. The computer program product of claim 4 , wherein the second memory section of the memory further comprises an interrupt summary vector with an interrupt summary indicator per bus connected module of a plurality of bus connected modules coupled to the plurality of processors to indicate whether there is the respective interrupt signal issued by a respective bus connected module to be handled, and wherein the forwarding vector further comprises a second set of forwarding vector entries, the second set of forwarding vector entries comprising a second forwarding vector entry assigned to the respective interrupt summary indicator, the second forwarding vector entry to indicate whether the respective interrupt summary indicator to which it is assigned is to be updated in order to indicate for the first guest operating system that there is the respective interrupt signal issued by the respective bus connected module to be handled, and wherein the method further comprises:
receiving another interrupt signal with another interrupt target ID, the other interrupt target ID identifying a second target processor for usage by the first guest operating system to handle the other interrupt signal;
checking that the second target processor is scheduled for usage by the first guest operating system; and
translating, based on the second target processor being scheduled for usage by the first guest operating system, the other interrupt target ID to another logical processor ID and forwarding the other interrupt signal to the second target processor to handle using the other logical processor ID resulting from the translating to address the second target processor directly.

8. The computer program product of claim 7 , wherein the receiving the interrupt signal is from a first bus connected module and the receiving the other interrupt signal is from a second bus connected module.

9. The computer program product of claim 8 , wherein the receiving the interrupt signal is by a bus attachment device from the first bus connected module, and the receiving the other interrupt signal is by the bus attachment device from the second bus connected module.

10. The computer program product of claim 7 , wherein the method further comprises forwarding based on the second target processor not being scheduled, the second interrupt signal to the first guest operating system using broadcasting, the broadcasting comprising selecting, by the bus attachment device, a selected second forwarding vector entry of the second set of forwarding vector entries which is assigned to the other interrupt target ID and updating the selected second forwarding vector entry such that it indicates that the respective interrupt summary indicator to which it is assigned is to be updated in order to indicate for the first guest operating system that there is the second interrupt signal to be handled.

11. The computer program product of claim 4 , wherein the first memory section further comprises a guest interrupt table, the guest interrupt table comprising a first set of guest interrupt table entries, the first set of guest interrupt table entries comprising a directed interrupt summary address indicator for each of the respective directed interrupt summary indicators of the directed interrupt summary vector with a respective directed interrupt summary address indicator indicating a memory address of the respective directed interrupt summary indicator in the second memory section, and wherein assignments of forwarding vector entries of the first set of forwarding vector entries are implemented using the guest interrupt table with each forwarding vector entry of the first set of forwarding vector entries being assigned a guest interrupt table entry of the first set of g

Assignees

• IBM

Inventors

• Raisch Christoph
• Kraemer Marco
• Schmidt Donald William
• Nerz Bernd
• Driever Peter Dana

Classifications

• G06F9/48

  Program initiating; Program switching, e.g. by interrupt · CPC title

• G06F9/4812

  by interrupt, e.g. masked · CPC title

• G06F13/24 Primary

  using interrupt (G06F13/32 takes precedence) · CPC title

• G06F9/5077

  Logical partitioning of resources; Management or configuration of virtualized resources (specific details on emulation or internal functioning of virtual machines G06F9/455) · CPC title

• G06F12/1081

  for peripheral access to main memory, e.g. direct memory access [DMA] · CPC title